Showing results for 
Search instead for 
Did you mean: 

FPGA : Get DutyCycle and Frequency

Hello everyone,


I want :

Using 7846R digital input, i want to measure on square signal Tup, Tdown and Period.

See my VI attached.


My problem :

I send Tup and Period to Windows Host to calculate Duty Cycle and Frequency.

My problem is that my frequency keep raising like it was a counter incrementing. I checked the code between, it is ok.

Can you find the issue ?



0 Kudos
Message 1 of 7

Does my question is not clear enough ?

My algo must be wrong but I can't say where it is...

0 Kudos
Message 2 of 7



Your problem is that you are putting out a number on every execution of this code whether or not an edge was detected.  In the case that an edge is detected you are putting out the time delta, but when no edge is detected you are putting out the reference clock time, which is probably not what you exepct.  And as both edged will never happen simultaneously, one or the other number that you want will always be wrong.



0 Kudos
Message 3 of 7

You might have seen my error but i still can't see it.

Every Up edge and Down edge, i save the associated time into shift register.

To be more specific,

* when booleans are TT or FF i send the last time which has been calculated.

* If TF it is Upping edge, i get the Upping time and save it into my shift register.

* If FT it is lowing edge and save it into my shift register.

You have to imagine booleans represent state at T0 and the other state T0+1.


Where is my mistake ?

0 Kudos
Message 4 of 7

Any update ?

0 Kudos
Message 5 of 7

When your case structures execute the TRUE case, you do indeed get the time delta you expect.  When your case structures executes the FALSE case you get the clock time, and the time delta that you want is lost.  Because of the way your boolean input logic is laid out only one of the case structions will execute the TRUE case during any single call to this subVI.  Therefore, one and only one of the numbers that you need for your calculation will be valid, the other will be garbage, and consequently your calculation will always be wrong.

0 Kudos
Message 6 of 7

Indeed my mistake.

But after correction, my duty cycle remain at 50% and frequency at Inf.

I send Data in 64bit type with FIFO DMA with timeout -1.

I get FIFO data with asynchronous VI. It appears that for frequency data sometimes, data is 0 which involve inf frequency...

See my correction attached

0 Kudos
Message 7 of 7