FPGA: Generate 'bit file' in LV and download it in Non-NI hardware

[amitwadje]

Hi,

I had worked on Xilinx FPGA for couple of projects using VHDL and Xilinx ISE SDK.

I never used LabVIEW FPGA development but I am well familiar with LabVIEW (Developed Instrument drivers and some automotive application before).

In our lab, we use Xilinx platform for FPGA development and want to migrate to LabVIEW FPGA.

After a lot of reading about LV FPGA related stuff, I concluded that

1. We can use ‘LabVIEW FPGA Development with only NI hardware.

2. There are few RIO modules available which uses Xilinx FPGAs.

My aim is to use LabVIEW for FPGA development without NI RIO hardware,

Now, my questions are(Based on theoretical thinking)

1. Practically, is it possible that we use LV to just simulation and generation of ‘.bit file’? And download the ‘.bit file’ into hardware using Xilinx kit?

 2. I see in tutorials they always select the RIO hardware as FPGA target but in Xilinx we always select Product family and Device.

     How about if I choose RIO hardware which has Xilinx FPGA (matching to my Non NI hardware) and generate the ‘bit’  file accordingly?

It will be great, if you can guide me through.

Thank you.

References,

LabVIEW FPGA Module Training for Xilinx Spartan 3E XUP Hardware

What kinds of FPGA does LabVIEW support?

Does LabVIEW FPGA support Spartan-3E (1600Kgate) kit?

[crossrulz]

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amitwadje wrote:  How about if I choose RIO hardware which has Xilinx FPGA (matching to my Non NI hardware) and generate the ‘bit’  file accordingly?

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It is not going to work.  NI adds a lot more to the code for talking to the available IO and for communicating with the host (whether it is Windows or an RT, via Ethernet, PXI, PCI, special bus that the cRIO uses, etc).  If you wanted to be adventurous, you could try to dig through all of the VHDL generated files and just take out the parts you want and compile those.  But it seems like it would be way more work than it is worth.

BTW, I remember when LV FPGA first came out and what you want to do is exactly what everybody thought it was.  Many of us were very sad when we learned it was only for NI hardware.

And all of NI's RIO hardware uses Xilinx.  And there are quite a few of them from PCIe and PXI cards, cRIO, and sbRIO.  From what you describe, the sbRIO is more likely what you would be interested in.

[amitwadje]

Hi Crossrulz,

Thank you for answer,

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crossrulz wrote: If you wanted to be adventurous, you could try to dig through all of the VHDL generated files and just take out the parts you want and compile those

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Interesting and will surely try with some code.

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is it possible do up to simulation by selecting any random RIO target hardware?

In VHDL we have synthesisable and non synthesisable statement, do we also have some in LabVIEW functions/VI like that?

also hope we can write a testbench code here.

Thank you...!!