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FPGA (FlexRIO) error -61046

Hi,

 

I get the following error sometimes:

 

"Error -61046 occurred 

Possible reason(s):

LabVIEW FPGA: An error was detected in the communication between the host computer and the FPGA target."

 

The sysstem includes Windows XP PC with Labview 2012 with a MXI-connected 1073 PXIe chassis, 7951R FlexRIO, and PXI 5752 Adaptor.

 

The error occurs:

1. When I open a VI calling FPGA program, and runs for the first time. If I run the same VI again, it runs without this error.

2. When I run the VI, stop it, and run again immediately(within 2-3  seconds). If I run it after taking some time, no error.

3. When I run a VI, stop it, and run another VI which calls another FPGA program(from same project or different project), it gives the this error, only on the first time running.

 

because of the third reason, I am unable to call more than one  FPGA program(one after execution of another ) in my application.

In the FPGA code I have SC Timed Loops, set to the 50 MHz clock of IO module(5752)

 

Please share any solutions/suggestions.

 

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Hi AJ, 

Can you provide your project, or at least your host code?  

Have you ever been successful running FlexRIO code?  

Does it generate the errors when using the 5752 examples as it does when running your code? 

 

National Instruments
FlexRIO & R-Series Product Support Engineer
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Here I am attaching my Host vi.

The main vi is ''forPost trigger_single Fifo_host.vi''.

 

 

The first FPGA code is called inside the "ADC Settings(Host).vi" , the FPGA code is for configuring the 5752 ADC digital gain, offset,and filter settings. I made that code from a 5752 example vi for ADC configuration.

it is running without giving any error and when I stop it, I am able to close the FPGA reference without generating any error.

 

Then the next FPGA vi is called, which is for reading the channels (of the ADC that was just configured). At the third read/write control node ('Rising Edge? , Post-trigger samples, Start), it gives the above mentoned error. 

 

If I run the main vi without calling the vi for ADC configuration, it runs properly.

 

In case of running example programs, the same problem occurs.  When I run a VI, stop it, and run another VI which calls another FPGA program, it produces this error, only for the first run.

 

**************

One more thing to mention,  when I try to compile a FPGA code, for the first time, compilation error -61330 occurs(after generating intermediate files). When I try again, it works.

 

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Please find the attachment here.

Download All
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As a work around, I had to integrate both the FPGA codes into a sngle VI.

 

But I hope that normally there would not be any problem in calling FPGA vis one after another.

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Hey AJ, 

At first I was thinking that it had something to do with the clock not being stable when you get to the read/write node.  If you open the example for the 5752 you'll see the init loop that goes True - False - True.  

Furthermore, the 61046 error message says the following: 

2013-02-13_161426.png

In this case, we are using an external clock, the 50 MHz from the FAM.  

 

But the fact that the main code runs if the ADC code doesn't disproves this theory.  

I'm wondering now if something odd is going on with the reset of the "Close FPGA VI reference".  Have you tried to put a reset function in your main code, after you've downloaded the new bitfile? 

 

Also, are you using the Init code from the 5752 example?  

snip1.png

 

 

National Instruments
FlexRIO & R-Series Product Support Engineer
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Yes, I was using the same Init code, found in example vi. And I tried it with both Timed while loop and normal while loop.

I have also tried resetting, after downloading the bit file. But it was giving the same error from the same point.

 

I am suspecting that there is something like the ADC settings that we configured in a FPGA code cannot be retained for another FPGA code, it will try to reset the ADC to default settings. That may be the reason it doesn't give error when I run it second time, because the ADC has been reset in the previous attempt.

I am not sure about it.

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Message 7 of 8
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hi AJ,

 

Actually, Am getting the same error as you have mentioned.

Can you mention what was the issue and have you identified it..

So, that I can fix my issue!!

 

 

Thanks in Advance.. 🙂

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