FPGA FIFO Read timeout even when set to "-1", changed behavior from 8.6 to 2009

[DarrenJones]

Hello,

I have a strange behavior on LabVIEW FPGA 2009 regarding target-scoped FIFO reads: 

timeout set to "-1"

still times out every ~107seconds (2^32 ticks at 40MHz)

This behavior was *only* seen after recompiling in 2009. Same code in 8.6 did not time out.  Is this a bug or known change in behavior from 8.6 to 2009?

thanks,

Darren

[Donovan_B]

Hi Darren,

This was reported to R&D (# 219811) and is currently being investigated to determine whether this is due to a change in LabVIEW FPGA or the Xilinx compilation tools.

When I tested this, I did not see a timeout every 107 seconds.  I only saw the timeout the first time the bitfile was run after being downloaded to the target or the first time after a reset.  Any subsequent runs or continuation after the first timeout did not cause another one.  Is this the same behavior that you are seeing or do you see it every 107 seconds?  If it only happens the first time, a possible workaround would be to put some logic before the first FIFO Read call to make sure that something is available in the FIFO the first time it is read.

[DarrenJones]

Donovan, thanks for the quick reply.  I am seeing a timeout every 107 seconds that expire while the FIFO is empty.  This timeout resets every time the FIFO is written to and read.  Example:

t=0

t=107 timeout occurs

t=214 timeout occurs

t=300 single element passes through FIFO

t=407 timeout occurs

t=514 timeout occurs

etc