01-26-2011 01:11 PM
Hi,
Probably a newbie question:
I'm writing a program with 8 cRIO modules.
It has an FGPA vi, an RT vi, and a Host vi.
I can easily read Inputs in the FGPA, build them into an array and put them in a FIFIO (Target to Host). This is read in the RT. Some are scaled and whatnot and then passed to the Host via TCP (actually the STM library). I'm not sure what the limit is, but I could probably pass dozens of inputs through the FIFO at one time.
What I can't figure out is how to pass a single Output back to the FPGA. Since I can't pass a cluster in a Host to Target FIFO to pass an address and a value, I would have to have a separate FIFO for every single output.
Should I create a cluster (or more) on the FPGA and use an FPGA Write Control in the RT to pass the address and the value, and then have one (or more) massive case statements to output to the proper address? Is there a better method that I haven't come across yet?
TIA,
Paul
01-28-2011 09:12 AM
Hi Paul,
Can you post your code, or a screen shot of your code so I can better see what you're talking about?
Thanks?
01-29-2011 09:37 PM
Paul,
You can actually use the same technique with the Outputs that you are using with the Inputs. You will need to use a different FIFO as the FPGA FIFOs only go one way. But you can use the same technique, build an array on the RT side, pass the data to the FPGA via FIFO and then index the array and output to hardware in the FPGA code. This technique can be used so that multiple channels can be updated and/or a dynamic signal can be generated.
Dave