[FPGA] ERROR:HDLParsers:3621 The basic identifier n_ is illegal because it ends with an underline character (VHDL IEEE 1076-2000 LRM 13.3.1).

[o_a]

Hello,

I am compiling a VI for FPGA target, and I have the following error:

ERROR:HDLParsers:3621 - "C:/NIFPGA86/srvrTmp/xxx.vhd" Line 62. The basic identifier n_ is illegal because it ends with an underline character (VHDL IEEE 1076-2000 LRM 13.3.1).

According to what I have read, it seems that this error is due to an error in the name of an object (ending with '_').

But VHDL code is generated by LabVIEW, so I cant modify it.

I haven't found any indication on which VI caused this error, so I don't know what I could modify to get this error away.

My configuration is:

- LabVIEW 8.6

- Xilinx ISE 9.2i

Here is an extract of the log file:

Regenerating IP...
Generating Implementation files.
Generating NGC file.
Finished Regenerating.
Successfully generated dualportramcorefromwfpgandatawready_2988faed39b1440.
Regenerating IP...
Generating Implementation files.
Generating NGC file.
Finished Regenerating.
Successfully generated dualportramcorefromwrtndatawready_043eda55fe9748e.

Release 9.2.04i Xflow J.40
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
xflow.exe -p xc2v3000-4-fg676 -synth vhdl_area.opt -implement balanced.opt
-config bitgen.opt C:\NIFPGA86\srvrTmp\LOCALH~1\PR90A9~1\toplevel_gen.prj 

Using Flow File: C:\NIFPGA86\srvrTmp\LOCALH~1\PR90A9~1/fpga.flw
Using Option File(s):
 C:\NIFPGA86\srvrTmp\LOCALH~1\PR90A9~1/balanced.opt
 C:\NIFPGA86\srvrTmp\LOCALH~1\PR90A9~1/bitgen.opt
 C:\NIFPGA86\srvrTmp\LOCALH~1\PR90A9~1/vhdl_area.opt

Creating Script File ...

#----------------------------------------------#
# Starting program xst
# xst -ifn toplevel_gen_xst.scr -ofn toplevel_gen_xst.log
#----------------------------------------------#
Release 9.2.04i - xst J.40
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
-->
TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  😎 Partition Report
  9) Final Report
     9.1) Device utilization summary
     9.2) Partition Resource Summary
     9.3) TIMING REPORT

=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "C:/NIFPGA86/srvrTmp/LOCALH~1/PR90A9~1/toplevel_gen.prj"
Input Format                       : VHDL

---- Target Parameters
Output File Name                   : "toplevel_gen"
Output Format                      : ngc
Target Device                      : xc2v3000-4-fg676

---- Source Options
Top Module Name                    : toplevel_gen
ROM Extraction                     : YES
RAM Extraction                     : YES
RAM Style                          : Auto

---- General Options
Optimization Goal                  : SPEED
RTL Output                         : YES
Read Cores                         : YES

=========================================================================

The following parameters have been added:
Optimization Effort                : 1

=========================================================================

=========================================================================
*                          HDL Compilation                              *
=========================================================================
[...]
Compiling vhdl file "C:/NIFPGA86/srvrTmp/LOCALH~1/PR90A9~1/case_092441b0_frame1_176b7178.vhd" in Library work.
Entity <case_092441b0_frame1_176b7178> compiled.
Entity <case_092441b0_frame1_176b7178> (Architecture <vhdl_labview>) compiled.
Compiling vhdl file "C:/NIFPGA86/srvrTmp/LOCALH~1/PR90A9~1/casesel_40f16dfc.vhd" in Library work.
Entity <casesel_40f16dfc> compiled.
Entity <casesel_40f16dfc> (Architecture <vhdl_modgen>) compiled.
Compiling vhdl file "C:/NIFPGA86/srvrTmp/LOCALH~1/PR90A9~1/XNode_h2dce1d0_n17e107bc_121d4b18.vhd" in Library work.
Entity <XNode_h2dce1d0_n17e107bc_121d4b18> compiled.
ERROR:HDLParsers:3621 - "C:/NIFPGA86/srvrTmp/LOCALH~1/PR90A9~1/XNode_h2dce1d0_n17e107bc_121d4b18.vhd" Line 62. The basic identifier n_ is illegal because it ends with an underline character (VHDL IEEE 1076-2000 LRM 13.3.1).
ERROR:HDLParsers:164 - "C:/NIFPGA86/srvrTmp/LOCALH~1/PR90A9~1/XNode_h2dce1d0_n17e107bc_121d4b18.vhd" Line 62. parse error, unexpected MINUS
-->

Total memory usage is 343240 kilobytes

Number of errors   :    2 (   0 filtered)
Number of warnings :    1 (   0 filtered)
Number of infos    :    0 (   0 filtered)

ERROR:Xflow - Program xst returned error code 6. Aborting flow execution...

[JérémyC]

Hello o_a,

Thank you for posting here,

If you have checked all you VIs and all of them work, I suggest you to check the names of all the variables too. Check if any of the variables contains other characters than letters (lowercase and uppercase) or numbers. Be careful to avoid any character else.

You can execute your VIs on the Development Computer with Simulated I/O first (before executing on FPGA), animate the execution of your VIs and add error clusters in order to check if there are no hidden problems.

Regards,

[o_a]

Thank you for the answer.

I have variables with characters that are not letters (lowercase and uppercase) or numbers. For exemple: ( ) + _ - and space.

But until now, I have not had this error.

According to the error message, it occured on file: "C:/NIFPGA86/srvrTmp/LOCALH~1/PR90A9~1/XNode_h2dce1d0_n17e107bc_121d4b18.vhd" Line 62.

But my design uses more than 160 VI, so I don't know which one failed (I have no file named "XNode_h2dce1d0_n17e107bc_121d4b18.vi").

It seems impossible to execute my VIs on the Development Computer with Simulated I/O. Maybe because à use DMA FIFO ?

Anyway, I have build my VI again without having this error.

So I don't know why this error has appeared and why it is now OK.