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FPGA Development methods

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I am currently trying to develop a waveform generator based on the LabVIEW example
 "NI 6585 Continuous Waveform Generation - Advanced.lvproj"
found in my
 C:\Program Files\National Instruments\LabVIEW 2009\examples\FlexRIO\IO Modules\NI 6585\

 

I am compiling for a FlexRIO PXI-7954R target.

 

The example take about 45minutes to compile and my modified version now takes about 75minutes to compile

 

This long cycle time between code change and trying it out means that it is very difficult to achieve any decent progress.

 

I was wondereing if there was another way of developing and debugging code for the FPGAs? For instance is there any way of running the VIs that are targeted for the FPGA in some kind of simulator ? Thus avoiding the long compile time?

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you can right click on the fpga icon in your project, select execute vi on -> development computer with simulated io.  There is a vi template for even simulated custom data.  There is an aption for simulating with real io but I have not tried this.  This will avoid the compilation time issues.  It is a good idea however to run the  compilation when you have down time you have the most recent so bitfiles and timing reports, I like to do this at night and when I go out to lunch (no productivity lost).
Paul Falkenstein
Coleman Technologies Inc.
CLA, CPI, AIA-Vision
Labview 4.0- 2013, RT, Vision, FPGA
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Another way around compilation times is to partition your code into pieces that can be tested without the rest of the application.  As an example, the application I'm working on now has communications, safety monitors, analog to digital and resolver to digital converters, PWM's, control logic, etc. which are all partitioned from one another.  Each partition is contained in its own subVI without diagram wires in or out.  I place each subVI in a diagram disable and then only enable the subVI's of interest at any given time.  This reduces the compile time to just the subsystem of interest, while not breaking the code for everything else.  From time to time, I'll turn everything on to make sure the design still fits the FPGA and clock rate.

 

I'm not familiar with the example code you're working with, but if it uses the LabVIEW memory constructs (project or local) you might consider turning the size down to the minimum you need to prove functionality.  These constructs take a long time for the Xilinx compiler to create, and the bigger they get the longer it takes. 

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