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[FPGA] Decreasing fractional interpolator real-estate?

Okay, this is a real long shot...

 

We have some FPGA code running on a PXI-5644R Vector Signal Transceiver and our design is limited by the required FPGA real-estate. The real bottleneck is the fractional interpolators we're using to upsample data to the full rate required by the VST which consume the lion's share of the FPGA. So the question is, has anyone solved this one, and can anyone give me any tips/pointers to get around this issue.

 

Some background:

1. This uses fractional interpolators provided by NI and we cannot drill into the interpolator code (it is locked).

2. The interpolators are running at the full FPGA clock rate of 120MS/s and have to obtain the required output sample rate, so there is no possibility of somehow multiplexing an interpolator to service multiple channels, so one is required per data channel.

3. We have blocks of 8 channels that all use the same interpolation parameters- so my thinking was that perhaps efficiency can be improved this way by creating an 8 channel interpolator and sharing some common code between them- however gut instinct leads me to suspect the majority of the resource is taken up by filters which cannot be shared?

 

As I say, just kicking the can around on this one. Thoughts/ideas?

 

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Sorry to say that I don't have any solutions, but just questions.

 

Why is it that you cannot just use a single interpolator block and need to have the different streams continuously being interpolated? Do you need to very quickly shift from one to another?

 

Any chance you can use DRAM to cache the interpolated waveform data?

 

What is your baseband data IQ rate?

 

I would think this is the case, but make sure the overclocking for the interpolator block is 3x overclocking (VST IDL 13.5 shipped with a 2x overclocking version of the interporlator block that makes it easier to meet timing, but uses more resources - but it is a user's choice).

 

Do you need access to the RF In channel from the same bitfile? If you can live without RF In (acquisition) access in the bitfile, you can remove the RF In signal chain.

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Hi JMota,

 

First off, thanks for the response and apologies for the delay in replying. Things have been somewhat hectic lately and this thread got temporarily forgotten. To answer your questions-

 

>Why is it that you cannot just use a single interpolator block and need to have the different streams continuously being >interpolated? Do you need to very quickly shift from one to another?

 

I need to produce multiple channels of output. This involves interpolating the data for the individual channels up to the fool sample clock rate of 120MHz and producing an output sample for each every clock cycle due to the VST architecture.

 

>Any chance you can use DRAM to cache the interpolated waveform data?

Not really - for reasons above.

 

>Do you need access to the RF In channel from the same bitfile? If you can live without RF In (acquisition) access in the bitfile, you can remove the RF In signal chain.

 

Thanks, this is a useful tip however we already cut that bit out.

 

>I would think this is the case, but make sure the overclocking for the interpolator block is 3x overclocking (VST IDL 13.5 shipped with a 2x overclocking version of the interporlator block that makes it easier to meet timing, but uses more resources - but it is a user's choice).

 

Don't think it helps in my situation, but this is a useful bit of info I wasn't aware of. Always useful to have up your sleeve!

 

 

 

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One thing I did was instead of passing values "from" and "to" to the routine, I passed the delta value instead.  This removed tha need to perform a subtraction.  Replacing all the other operations with high-throughput got me working for the rest.

 

I created a fractional interpolator and then converted it ti a VI and made modifications.  The calculations done within (although mathematically correct) can be simplified if you have a known output form (you can pre-calculate the delta values).

 

PS This is assuming we're talking about the same function......

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Once again some great tips there, unfortunately this NI VI is locked, so my options are limited.

 

As I said, there is probably no workaround for this one, although I have learnt a trick or two from this thread.

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Apologies in advance for asking a dumb question, but since the 5644R has a single RF Out channel, why is it that you need to have multiple data channels concurrently interpolated? Are you combining them somehow after the interpolation?

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The optimal solution depends on a few factors.

 

1.  How many channels are you interpolating?  I saw that you have blocks of 8 channels.  How many blocks do you have?  Do all of the blocks have the same interpolation factor?

2.  What is the sample rate of the narrowband channels?

3.  What is the channel spacing?  Are all of the channels equally spaced?

 

Unfortunately, the fractional interpolator is the only interpolation IP in the DSP IDL.  You are correct that there would be resource savings if the IP supported multiple channels (which it currently does not).  A different architecture could result in more resource savings though.

 

I may be able to point you to a more optimal solution once you answer my questions.  Your answers could also direct future enhancements in the DSP IDL.

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