LabVIEW 2016 FPGA
For a newly opened VeriStand Custom FPGA project, the Communication Loop displays this.
On what do these 15 elements refer?
According to this NI-page, the DMA_READ must be only as large as the number of packets of the elements read by the FPGA.
Also, the DMA_WRITE must be only as large as the elements writen by the FPGA, right?
In the sample project, however, the DMA_READ has 15 elements and DMA_WRITE 21.
Can anyone explain this?
The white paper you are referring too, under the section communication loop states "The DMA_READ FIFO is defined in the Project Explorer, and its depth must be specified to have at least as many elements as packets sent each iteration" and similar for DMA_WRITE.
If the FIFO is less than the number of packets sent/received each iteration of the PCL then data will be lost either on the FPGA or VeriStand side. The assumption with 15 is simply that it is currently configured for 15 elements however if you plan to make changes such as adding in 8 new digital output lines, you will then be sending 19 packets per iteration, if still configured for 15 then each iteration you will always be 4 packets off and this will result in mangled data and strange behaviour.
Essentially, plan out how much data will be passed back and forth with the FPGA each iteration of the PCL and then set the number of elements of your FIFO to this size.
OK, last question: If I want to read 50 packets from the FPGA then the DMA_READ have to be 50 elements?
If I want to write 60 packets to the FPGA then the DAM_WRITE have to have 60 elements?
You are correct, or rather they need to be at least, there is nothing stopping you from making them greater in size of elements than the number of packets you plan to read/write.
Writing Custom FPGA/Device for VeriStand can be a complicated task. I would recommend to have a skim through the CompactRIO Developers Guide first to get some familiarity with FPGA: