FPGA - Component level IP access FPGA I/O

[HettmannAlex]

Hello! 

I am planning on writing an application to PXI-7842R board which emulates a sensor. It would communicate with a microcontroller over SPI protocol. The task is the following: the application waits for the commands which instruct the sensor (about 15 member command set) and sends the proper response (product information, status, measured signal etc.). I have studied the spi example using the LabVIEW FPGA module but using those methods I was not able to reach the desired 8 MHz clock rate. So I decided to integrate a high speed SPI core written in VHDL into my FPGA VI. As I do not have any eperiences in using Component Level IPs, I have several issues now. Firstly I would like to know if it is possible to connect the FPGA I/O pins directly to the IP ports. In the CLIP tutorial I read something like it supports accessing FPGA I/O. Could you tell me how to realize this?

[David-A]

You can't use socketed CLIPs on R series devices.

The 7842R supports DIO line rates up to 40MHz. So theres nothing preventing you from using existing SPI examples or writing your own that can run at 8Mhz using only LabVIEW FPGA.  

If you find writing VHDL easier though you could try instantiating you SPI IP as a user defined CLIP then attach the outputs and inputs to the IO nodes on the FPGA block diagram.