Mauritius,
Sorry in the delay in posting back to you. I must have missed the notification for your previous responses.
As far as I can tell, there is a bug in the Xilinx compilation tools that specific designs (like yours) cause to surface. Unfortunately, I haven't been able to reproduce the problem in any compilations. Without a reproducing case, I can't well report the bug to Xilinx.
It's is however possible that the bug will have been resolved in newer versions of the compile worker. Once LabVIEW 2013 releases, you might consider trying to compile the FPGA VI through the newest version of the tools for linux to see if the problem has been resolved.
If at any point you can provide your design, (or a reproducing design that you can release) I'd be happy to take the appropriate action to report the bug.
Regards,
-Nick-
Nick C | Software Project Manager - LabVIEW Real-Time | National Instruments
