Attempting to compile even simple FPGA VIs is returning in failure for me, and I'm not sure why. This is on windows 7, 32 bit, Xilinx 14.4, LabView 2013, for sbRIO-9632.
"Some signals were not properly constrained in the design." in the summary.
"Failed to load library libPort_ExecLoader.dll because of The specified procedure could not be found." in the Xilinx log.
Can anyone help? Many thanks!
Are you compiling on your local machine or on a remote machine? I would recommend repairing or reinstalling the Xilinx tools on your local machine and any remote machines being used.
Thanks for replying! Yes i am using a local machine, not any remote. I saw it mentioned somewhere that there might be a specific order that things need to be installed in, is this true? If so, what is the order they should be installed/reinstalled? Thanks!
When installing software you should follow this installation order: LabVIEW >> LabVIEW FPGA Module >> compile tools >> device drivers. I'm including a link below to a document that describes the installation process. Hopefully this information is helpful!
RELEASE AND UPGRADE NOTES
LabVIEW FPGA Module
Thanks much, i'll try uninstalling everything and reinstalling in that order. Hopefully this fixes it. Will post back once tried.
You are very welcome Daniel!
Hello everyone !
I use a cRIO-9103 for my project and I attempted to compile a new VI for the FPGA. The former code compiled without problem, but the new one failed with the error "Some signals were not properly constrained in the design". I read the issue that was given in this topic, but the strange thing is that I just added a while loop in my old program to make my new one.
I joined to this message the new programm of the FPGA and the Xilinx log (I use Xilinx 10.1). The While Loop which causes problems is called "Traitement des informations envoyées par la centrale inertielle (IMU)". Can someone save me please ? ^^
Do you get this error now when trying to compile any VI or only on this particular VI? If you remove the while loop, can you compile the VI? Have you tried reinstalling the software?
Thank you for replying Joshua-B !
I tried to erase the new while loop, and it compiles. Consequently I think that the code tha I added does something wrong. I'm not an expert in FPGA programmation, so I don't know if my design is entirely compatible with the component.
I erased the memory of the FPGA and I re-installed all the softwares on it (Labview, modules, etc ), but it had no effects.