FPGA CRio not giving proper digital outputs

[ErnestoB]

I'm working on an fpga project with the compact RIO. I tried following the youtube tutorials and written out tutorial but i'm not getting any similar results in FPGA scan interface. 

I attached my project. Here's the signal i get from the basic VI, which is a digital IO set as an output in a while loop. Along with that there is a for loop to basically change the frequency of the digital signal up and down. But whatever number I put in for the for loop, it gives me the same frequency. 

My thought process goes like this: if the CRio has an optimal processing time of 40MHz than a for loop that cycles 400 times should give me an oscillation output of 100KHz, which it's not no matter what number I put in. 

Any help is appreciated. 

Thanks. 

[Jacobson-ni · Accepted solution]

LabVIEW is almost certainly compiling that for loop out as dead code (nothing is happening so LabVIEW gets rid of it). I would recommend using the loop timer function if you are looking to change the frequency or put everything in a Timed Loop. Everything in a timed loop will execute in one tick.

[GerdW]

Hi Ernesto,

to put it in other words:

If you want to wait for a certain amount of time you need to use a wait function to wait that amount of time!

[ErnestoB]

Thanks guys. Looks like Jacobson was correct. Labview was compiling it as a deadloop and seemed to be skipping over it. 

Here's a pic of the corrected loop. Not sure if it's good practice to do it this way or not as it's not giving me the expected frequency (it's giving me 1.67MHz). 

[GerdW]

Hi Ernesto,

what about using some dedicated timing function when you want a precise timing in your loop?

Did you read my last message?

Here's a pic of the corrected loop.

The compiler still might remove the FOR loop as it is static code…

Not sure if it's good practice to do it this way or not as it's not giving me the expected frequency (it's giving me 1.67MHz).

I don't know where you learned to use "CPU burning FOR loops" to create some kind of timing - and surely this is "no good practice"…

I heard of this use case back in the early 80's of the last century: at that time the CPU speed was well known and the compiler output too - you could create a reliable loop timing by iterating an empty FOR loop several times. But now this is more than 30 years ago and you don't use an old 8086 CPU!

Again: when you want to have a precise timing in your FPGA loop you need to use some timing functions!