FPGA- 25MHz CLOCK SIGNAL IN A DIGITAL I/O

[AsunaM]

Hello all,

I would like to generate a clock signal (square signal 3.3V) at a Digital I/O on a sbRIO 9632.

I tried this:

- Make a single cycle timed loop at 50MHz (derived clock)

- Put into a stacked sequence structure, when 0- the port becomes TRUE, when 1 the port becomes FALSE.

- Insert all in a while loop.

This program at the FPGA program but externally to the "main" program in the same .vi (because I need it works all the time). Also the FPGA program is the fpga top level of the SPI multiport Example and is a stacked sequence structure.

I don't know what I'm doing bad but I can't see the clock signal at the oscilloscope.

Always the port it's "true".

Could you help me?

[Spectre_Dave · Accepted solution]

I use a SCTL running @ 20MHz to generate a 10MHz clock.

All you need is a SCTL with an Invertor on the IO Line and shift registers to hold the last state of the IO.

Each time the SCTL runs the IO is inverted and output. You should be a 50% Duty Cycle Clock.

[sendia]

In addition, according to the sbRIO specifications (http://www.ni.com/pdf/manuals/375052c.pdf), the Maximum tested DIO frequency is 10 MHz (page 36). Change the loop frequency to achieve this parameter and then check in the scope if it is generated properly.

[AsunaM]

Thank you so much!!

And sendia, you could generate more than 10MHz but your wave would be less square than at 10MHz.

Anyway thank you for reply! 🙂

[sendia]

Hi AsunaM

Yes you can but it is not guaranteed. Indeed, the 10MHz is not the update rate but the output frequency which means you can write at least at 20MHz:

http://digital.ni.com/public.nsf/allkb/160A6C26C8B25B998625761A007D80FB?OpenDocument