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FIFO overflow issue when plotting xy plots in real time(FPGA

I try to plot xy plot using "xy graph".

For that, it transmits several analog signals to the HOST PC through FIFO of FPGA module.

At this time, overflow occurs in the FIFO by xy plot when a certain period of time passes.

What a method can i use to solve this problem?

 

For reference, I tried increasing the waveform size, but the overflow occurs inevitably.

If xy plot is canceled, overflow does not occur.

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There is too much data coming in from the FPGA. One benefit of an FPGA is to reduce the amount of data. Do you need all of the data?


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Only 2 out of 6 data plot xy graph.

And procuer-consumer loop is used and only 2 data are transmitted by queue.

however, overflow occurs after a long time(about 120sec).

Note that sample rate is 1 msec and waveform FIFO size is being increased from 50 to 250.

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