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FIFO in FPGA for ultrasound

Hello, I´m Mike and i would like to ask you for help.

I´am making a small "Myrio robotic car" and right now i would like to implement ultrasound. So i read that i need to use FPGA. I did it.(pic1) from ultrasound VI by NI. Then, i builded it, and ran it, everything was/is working. After that i wanted this results "time of flight" implement into "host VI". (Now i know that i did it probably by wrong way, but it´s working, pic2)..


And here i need help. Like you can see there is simple digital output for LED (just for trying, i didnt want to run car program with webcam and all things every time) and this loop will give me "outerror" that FPGA is running and if i understand that correctly, that is because this while loop cannot be executed in the same time like fpga. Ok, before i decided to write here, i googled and read some posts, pages etc. I learned that i need to use FIFO (correct me if i´m wrong). I did some example programs (and this)  witch ones did work well..i learned about FIFO, i made my own by this tutorial and i worked, but i have to admit that my knowledge is not on the level that i can implement this on ultrasound with two loop yet. (or maybe there is another way how to share this value from fpga)


All things together, i would like to implement FIFO on unltrasound FPGA but i could use some help with this because so far I´m not able. Please, i´ll be really grateful for any advice or if someone could modify VI for me. 


Thank you , Mike.

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Message 1 of 7

Ok so here is the one you requested. I have uploaded to my version. Sorry about the missing file.



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If you right-click the error on the FP, it will tell you it can't open a new FPGA reference because one is already open to the device.


Do you have the FPGA code running in interactive mode (with the FP open)?


If so, you might need to stop that one first before running the software.  You can re-create the UI in the code which is currently giuving you the error, reading and writing all of the controls on the FP.

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Interactive mode:

It's when you have a FP on your FPGA code and shoose to "run it" from the IDE (while on the FPGA target).  If the bitfile is up to date, LV will try to connect to the hardware (if the target is correctly configured in your project) and present the FP of the running FPGA code to you in real-time.  This is a great way to debug directly on the FPGA target (not really, there's a lot of abstraction done in the background, but it feels like you're debugging the FPGA directly).


If you have this running, it requires the hardware underneath. It will then prevent you from connecting to the same hardware from a RT "Open FPGA bitfile" function.  IT seems like your RT code has problems deploying the code because there is already a reference to your hardware used in the system.  Finding out who or what has this reference open is the key to solving your problem.  I just thought it might be the interactive mode of the FPGA code.

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@MikeTr wrote:

When you say this, what exactly do you mean? How did you validate that the FPGA program works?



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