I am using LabView 8.0.1 with the FPGA module 8.0.0. I have noticed a problem where I will copy a FIFO in the project explorer (usually by selecting the FIFO and holding control as I drag). The new FIFO appears and seems to inherit the same parameters as the original FIFO, except for the name, as expected. In particular, I need the FIFO to inherent the "never arbitrate" option as all of my FIFOs are used in single-cycle timed loops. The problem happens when I try to place the new FIFO inside a single cycle timed loop, I get a pre-compile arbitration error. It is not clear if it is the original FIFO arbitration that is incorrect or the new one. According to the FIFO properties dialog the arbitration is correct, but the vi won't compile.
My fix is to set the arbitration to something else, click OK, and then set it back to "never arbitrate" for all FIFOs in the vi. Then everything compiles without a hitch. Is this a known bug?
Cheers,
Daniel
