FIFO across clock domains

[Intaris]

No. If your FIFO is BRAM then my idea is wasteful In that regard.

But my proposal was simple BRAM read and write not a FIFO gor the delay part. This has minimal fabric overhead.

[Dragis]

There are good bits of advice in the replies so far.

I would summarize by saying that very few things in LabVIEW FPGA (or with these Xilinx FPGAs in general) can run at 500 MHz. In general, 250-300 MHz is about the max you'll be able to safely achieve on a regular basis, and only with a good deal of thought with how the design is layed out.

I would suggest trying to pack the data into a wider FIFO if possible so you can reduce the clock rate. It is unfortunate the local FIFOs do not support the mult-element read/write capabilities of the DMA channels. If they did, you could have the read and write sides push and pop different numbers of elements giving you more freedom to choose the appropriate clock rates.

[Thoric]

Some interesting observations:

Using a FIFO without the counter, I can cross clock domains successfully, but I cannot have a very large FIFO size (BRAM). Anything more than about 150,000 elements fails to compile with an obscure error, even though the resource usage at 150k elements is very low.

If I switch to using a small FIFO to cross the clock domain and then use a local BRAM block in the 500MHz domain I can create buffers much much larger than the FIFO allowed.

This tells me the FIFO BRAM implementation is very different from reserving direct BRAM memory. So I'm currently favouring Intaris's suggestion.

I need to cross into a third clock domain later, which will use the same technique as above. I'll keep the thread updates with any interesting findings...

[Dragis]

@Thoric can you explain a bit more about your application? The BRAM FIFO (especially the ones using the Built-In option) are essentially just a BRAM with a small amount of wrapper logic to handle the memory like a circular buffer. The observations you are seeing don't seem to map well to the intended implementation. 

What data type are the elements in the FIFO? What clock domains on the Reads and Writes have you tried?

If you can attaching some of the Xilinx logs results might be helpful.