FIFO DMA host question

[crossrulz]

All setting up, including the configure, should be done before the loop.  Likewise, any cleanup, like Stop, should be done after the loop.  So what you are left with inside of the loop is the read or write.

[RavensFan]

Of course.  Is there any logical reason you would reconfigure something repeatedly to the same values?

[FraBaggio1]

Thank you for the tips. I'll try to put 'configure FIFO' outside the loop, but I am not sure that this will help me regarding the correct counting. Actually at 20 MHz ( with 'configure FIFO' inside the loop) the counter works perfectly. At 40 MHz (see PDF attached) the counter works properly until the FPGA FIFO buffer (what is the reason?), but in correspondance of the FIFO buffer size there is a big jump (as at 20 MHz) and a lot of small jumps (absent at 20 MHz) preventing the counter counting properly.

How can I solve this? What If I increase the requested depth of Host FIFO buffer?

Thank you very much

Francesco

[crossrulz]

What else is happening in your host loop?  If there is something in there slowing down the loop, that needs to be moved.

Increasing the depth will just be delaying the issue.  You either need to read more samples at a time or speed up your read loop.

[FraBaggio1]

Hi,

thank you for the quick reply.

Attached you can see the host .vi. How can I change it?

[crossrulz]

Still not sure if everything in the loop is being shown.  I see where you are trying to get the loop rate.  Do you know what you are measuring for the loop rate?

And did you move that Configure out of the loop?  I know that could slow things down.

[FraBaggio1]

Hi,

attached is the entire host. The 10 cycle times are quite fast (30-40 ms).

Today I can't use labVIEW to modify the FIFO configure.

Thank you

[crossrulz]

Yeah, your loop needs sped up.  At 40ms per loop, you are generating 1.6M samples per iteration of this loop.  At the 30ms per loop, that is 1.2M samples.  And for that 60ms loop interation, 2.4M samples.  You are just reading a little over 1M samples.  To get 1M samples, it should take the FPGA 25ms at the 40MHz.  So you are easily overrunning your FIFO.

Some ideas to speed it up

1. As already mentioned several times, move the Configure to be before the loop.

2. Since you know how many iterations you want to take, use a FOR loop.

3. If you want to keep your loop rate information, autoindex the value instead of using the Build Array.  When you switch to a FOR loop, LabVIEW can preallocate the array.  This would also mean moving the indicator to after the loop.  It is not like you can really see the 40ms updates.  Even the 332ms it takes to run you will not likely notice.

[FraBaggio1]

Hi,

If I understand well the goal is to reduce as more as possible timing loop iteration in order to generate less samples (less than 1 MSamples) allowing reading on the host to be slower. To avoid data loss which is the ideal value for Msamples generation?

Thank you

Francesco

[FraBaggio1]

So the problem is that I am generating more samples than the host buffer (that is in my case1Msamples=2^20). Is it right?