FIFO DMA host question

[reffahcs]

I have a PXIe-5644R and I'm using the default streaming example (in LabView 2015) to add some FGPA code for FFT processing. I've added the code from the P2P example which seems pretty straight forward, but I'm having trouble on the host side.

I'm sure I'm missing some basic step, but when I add the invoke method to the host code and click on Method to select the DMA FIFO, I don't see the FIFO listed. It exists in the project and I'm writing to it on the target/FPGA side, but I can't get the host side to see it. I've tried saving the project, generating intermediate files and currently in the middle of rebuilding the bit code hopeing that will fix it, but I'm wondering what I'm missing?  The help file really doesn't go into anything beyong saying to use the invoke method and select the FIFO method.

I looked at the NI videos here: https://www.youtube.com/watch?v=uZ1hC8zKw-g but they gloss over actually creating the read FIFO on the host side.  I've been using the P2P FFT Co-Processor code for reference and everything looks like it should be working in the streaming example, but currently I'm lost trying to read my DMA FIFO on the host side.

Any help would be appreciated.

-Tim

[arevh]

Hello Tim,

It will be much easier to help you if you share your code, or at least the part implementing FIFO functionality.

If you have created the FIFO in the project (Target to Host), compiled the FPGA code, and opened the reference to FPGA VI properly, you should be able to access it.

Thanks,

Arev

CTO | RAFA Solutions

[crossrulz]

Try just dragging the DMA from the project to your block diagram.

Also make sure your DMA is setup to be Target To Host and you have the FPGA reference based on your latest bit file.  It is likely the DMA just is not in the interface reference.

[nathand]

You're sure you created a DMA FIFO, and not a target-scoped FIFO, right?

[reffahcs]

You all hit the nail on the head. I was incorrectly referencing the FPGA in the invoke method.

This is what I was trying to do, and I had incorrectly assumed that grabbing the FPGA reference would satisfy the invoke method needs. However as you can see, the FIFO I created did not show up.

I modified the code to what is shown in the image below, and now I can access the FIFO I created. Originally I didn't do this because I thought I would be opening two references to a single device (the PXIe-5644R), but that doesn't seem to be the case? So everything looks good now, I have some timing constraints that aren't being met on the FPGA side, but that's a different set of problems that I will start working through 🙂

Thanks all for the quick responses, slowly but surely I'm getting the hang of this 🙂

-Tim

[nathand]

Sounds like your FPGA Reference - at least the one in the cluster - was defined as an interface (a list of the front panel items, FIFOs, etc that the FPGA VI supports), and you created it prior to adding the DMA FIFO to your project. If the interface isn't linked to your FPGA VI, then it won't update with new items (such as FIFOs) that are added later, so you'll need to update it manually. You can do that by opening the cluster containing the FPGA VI reference and right-clicking to modify it.

[reffahcs]

That's absolutely the case. I used the standard VST Streaming code/template from Labview and then added a new FIFO to dump my FFT'd data into. I was assuming there was something I had to do to "resync" my project so my code would recognize my FIFO, but what exactly that process is isn't mentioned in any of the documentation I found.

I will look into what you mentioned about updating the cluster.

-Tim

[FraBaggio1]

Hi,

I implemented a simple counter in FPGA target. Via a FIFO, counter data are transferred to host target. No data is lost (i.e. buffer FIFO in the host stores all the counter data without losing them) when FIFO in the FPGA is written at 5 MHz,10 MHz (like in the figure of the PDF) or 20 MHz. However at 40 MHz, host buffer does not count properly and there are some numbers missing (for example 1, 2,3,4, (5 missing), 6,7,8,9, (10 missing) etc, 1 out of 5 numbers there is a missing number). This data loss happens only at 40 MHz. How can I do to solve this problem?

Thank you,

Francesco

[RavensFan]

What do FIFO4 and FIFO6 have to do with each other?

Why are you reconfiguring the depth of FIFO 6 on every iteration of the while loop?  You never actually change the depth, but I wonder if that reconfiguring is causing the FIFO to reset and you lose an element.

[FraBaggio1]

So FIFO6.configure should stay outside the while loop?