I'm running into errors trying to use example VIs to generate FPGA code to implement digital filters. These are taken straight from the examples (in NI example Finder, using directory structure, going to: Digital Filter Design/Multirate/Fixed-Point Filters/Generate LabVIEW FPGA code...) but I run into invalid input errors. A couple of these are attached with typical inputs. I've tried all sorts of different inputs but I can't put my finger on the issue. Does anyone see what's going on here? The VIs return 'inf' as the maximum sample input which seems odd. As example VIs I would have expected these to run without modifications under the hood.
Solved! Go to Solution.
Would you mind re-saving those VIs targeting LV 2017? We don't have a 2019 install, but I'll take a look if you can convert them.
Sure thing - here they are for LV2017.
I installed LV2019 along with associated FPGA module and RIO drivers and devices. I was unable to re-create your error.
1. I created a blank LVFPGA 2019 Project, and added an arbitrarily chosen FlexRIO target, the PXIe-7971R.
2. Added "Generate LabVIEW FPGA Code for Moving Average Filter.vi" to My Computer (not to the target).
3. Executed the VI using the default parameters.
4. VI executed without any issues. Result "Maximum Input Fs@40 MHz FPGA Clock = 10 MHz"
5. Opened the resulting project that was generated, and I don't see anything strange.
I repeated those steps with Multirate Filter.vi and got "Maximum Input Fs = 1.0526MHz".
This was performed with a clean install of:
I didn't have FlexRIO installed so I went ahead and tried with it installed. Also tried to put the VI in a project as you suggested.
I'm still getting the same error as before. Perhaps it's time for a re-install.
I have attached the basic project I used to test the VIs you posted. I created two folders inside the root directory to hold the resulting LVFPGA filter projects. I have left those projects resident in those folders, but you can clear them out to try and test on your own computer.
Thanks for sharing the project.
It still didn't work at first. But then I tried 32-bit LabVIEW to see, and then it finally worked! Tried again with my original VIs and they worked as well (no need to have them in a project with a FPGA Target).
So it seems this is an issue with something not working right with 64-bit LabVIEW... which is very odd since the examples were pulled from 64-bit LabVIEW.