ERROR: [Synth 8-5809] in FPGA Complation

jiangliang · ‎12-13-2019

Hello:

When i'm using FlexRIO with Cameralink 1483, I got a xilinx compile error says Error 8-5809.

I can successly compile some simpler VI in the same project, and the failed one is only using more resource, more logic, no odd things like CLIP or XIP has been added.

And the log says there are problem in interface.vhd, I checked this file and it a file comes with LabVIEW FPGA, encrypted, can't say there is anything wrong with that.

I compared the Interface.vhd of a working VI, the difference is working VI get me a Interface.vhd of bytes = 28752, and the one with error have a Interface.vhd bytes = 38240? Is this the reason my VI fail to compile? I did add 5 FIFOs in VI-scope to add some function, Also I added 4 FIFO to host (which should be fine since FlexRIO Controller should have 16 or maybe more DMA channel).

Can anyone give me some advice? Thanks!

Here is the compile result:

LabVIEW FPGA: The compilation failed due to a Xilinx error.

Details:
ERROR: [Synth 8-5809] Error generated from encrypted envelope. [C:/NIFPGA/jobs/K0WSe4L_wgI55K2/Interface.vhd:445]
ERROR: [Synth 8-5809] Error generated from encrypted envelope. [C:/NIFPGA/jobs/K0WSe4L_wgI55K2/Interface.vhd:446]
ERROR: [Synth 8-5809] Error generated from encrypted envelope. [C:/NIFPGA/jobs/K0WSe4L_wgI55K2/Interface.vhd:447]
ERROR: [Synth 8-5809] Error generated from encrypted envelope. [C:/NIFPGA/jobs/K0WSe4L_wgI55K2/Interface.vhd:448]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 385.238 ; gain = 154.605
---------------------------------------------------------------------------------
RTL Elaboration failed
2 Infos, 0 Warnings, 0 Critical Warnings and 5 Errors encountered.
synth_design failed
::RTL Elaboration failed
while executing
"source -notrace {C:/NIFPGA/jobs/K0WSe4L_wgI55K2/.Xil/Vivado-22556-Laptop-G7/realtime\SmallBlockTop.tcl}"
invoked from within
"synth_design -keep_equivalent_registers -top "SmallBlockTop" -part "xc7k410tffg900-2" -flatten_hierarchy "full""
(file "C:/NIFPGA/jobs/K0WSe4L_wgI55K2/synthesize.tcl" line 31)
invoked from within
"source "C:/NIFPGA/jobs/K0WSe4L_wgI55K2/synthesize.tcl""
# exit
INFO: [Common 17-206] Exiting Vivado at Fri Dec 13 15:28:43 2019...

Compilation Time
---------------------------
Date submitted: 12/13/2019 3:27 PM
Date results were retrieved: 12/13/2019 3:28 PM
Time waiting in queue: 00:08
Time compiling: 01:05
- Generate Xilinx IP: 00:00
- Synthesize - Vivado: 00:56

-------------------------------------------------------------------------------------------------------

and there is the Xilinx log:

WARNING: Default location for XILINX_VIVADO_HLS not found:

WARNING: [Common 17-306] Update version (2017.2.1_AR70173) does not match product version (2017.2.1).

WARNING: [Common 17-306] Update version (2017.2.1_AR70069) does not match product version (2017.2.1).

WARNING: [Common 17-306] Update version (2017.2.1_AR69663) does not match product version (2017.2.1).

****** Vivado v2017.2.1_AR71289_AR70173_AR70069_AR69663_AR69485 (64-bit)

**** SW Build 1957588 on Wed Aug 9 16:32:24 MDT 2017

**** IP Build 1948039 on Wed Aug 9 18:19:28 MDT 2017

INFO: [Common 17-1460] Use of init.tcl in C:/NIFPGA/programs/Vivado2017_2/scripts/init.tcl is deprecated. Please use Vivado_init.tcl

Sourcing tcl script 'C:/NIFPGA/programs/Vivado2017_2/scripts/init.tcl'

# package require struct::list

# package require struct::set

# set_param synth.elaboration.rodinMoreOptions "rt::set_parameter max_loop_limit 1000000;"

# ::struct::set add vhd_files [glob *.\[vV\]\[hH\]\[dD\]]

# ::struct::set subtract vhd_files {"BuiltinFIFOCoreFPGAwFIFOn0.vhd" "BuiltinFIFOCoreFPGAwFIFOn1.vhd" "BuiltinFIFOCoreFPGAwFIFOn11.vhd" "BuiltinFIFOCoreFPGAwFIFOn5.vhd" "BuiltinFIFOCoreFPGAwFIFOn6.vhd" "BuiltinFIFOCoreFPGAwFIFOn9.vhd"}

# read_vhdl $vhd_files

# if {[llength [glob -nocomplain *.\[xX\]\[dD\]\[cC\]]] > 0} {

# set CoreXDCFilesFH [open CoreXDCList.txt r]

# set xdc_files_xci [split [read $CoreXDCFilesFH] "\n"]

# close $CoreXDCFilesFH

# set xdc_files_all [glob *.\[xX\]\[dD\]\[cC\]]

# set xdc_files_source [::struct::set difference $xdc_files_all $xdc_files_xci]

# set xdc_files [read_xdc $xdc_files_source]

# foreach xdc_file $xdc_files_xci {

# if {[file exists $xdc_file]} {

# lappend xdc_files [read_xdc -ref [file rootname $xdc_file] $xdc_file]

# }

# set_property PROCESSING_ORDER {LATE} [get_files $xdc_files]

# }

# read_edif [glob *.\[eE\]\[dD\]\[fFnN\]]

# read_edif [glob *.\[eE\]\[dD\]\[iI\]\[fF\]]

# read_checkpoint "BuiltinFIFOCoreFPGAwFIFOn0.dcp"

Command: read_checkpoint BuiltinFIFOCoreFPGAwFIFOn0.dcp