Dynamic choice of FPGA I/Os

[cbutcher]

Hi Gryffin, 

If I create 16 different controls of channels i.e. Mod1/AI0, Mod2/AI3, etc.

And then create a case structure of 16 different cases being 1 channel, 2 channels, etc.

And then use local variables created from all of the controls for each case, I can dynamically select how many channels to use and which channels to assign!

Please let us/me know if you manage to compile that. From the way you've described it, I feel like a complaint about dynamic references is likely...

[Gryffin]

I can indeed compile dynamic I/O FPGA references as described for a cRIO-9040 and 3x NI-9238 cards!

[rolfk]

I solved this a bit different with an sbRIO-9651 and a custom analog front end. There are eight simultunaous sampling 8-channel ADCs connected through SPI channels to the FPGA. One loop acquires the data from the SPI lines one channel per iteration and puts them into a BRAM address. This was anyhow necessary since the order of the ADCs was pretty random in respect to the actual sensor channels due to layout and other constraints. Here I descramble the ADC input channel order back into the real sensor channel order. The BRAM also allows to have some extra buffer as it can store up to 512 64-channel frames.

A second loop reads the 64-channel frames from the BRAM and puts them into a DMA FIFO to transfer to the RT host. This all works perfectly reliable with 64-channels at up to 70kS/s and only uses about 40% of the FPGA fabric so far. Next step is to add some threshold circuitry in the FIFO loop that only transfers data to the FIFO when at least one of the channels reaches a programmable threshold value and then with up to 256 pre and posttrigger samples per channel and of course restartable so when a new trigger happens while still streaming, the post-trigger interval is reset.The FIFO loop is fast enough to catch up with those 256 samples in a short time when a trigger event occures after some inactivity.

There are other loops to generate the ADC SPI timing signals and one to generate a programmable sample clock that can also be synchronized with a simplified programmable fractional integer PLL circuit to an external quadrature encoder signal.