12-17-2019 10:08 PM - edited 12-17-2019 10:09 PM
Hello all,
I have a question about LabVIEW FPGA coding.
So I have a cRIO-9040 and I also have 4x NI-9238 cards.
I am essentially writing code that takes voltage measurements utilizing the 16 channels of the 4 cards.
I would like to dynamically select which inputs are being used by the measurement, instead of hard coding which inputs to use.
Instead of having to make a case structure with every single possibility for 16 channels (65,535 possibilities) like this:
I would like to just specify on my PC application: Mod1/AIO, Mod1/AI3, Mod3/AI2, etc.
Is there some way to do this that I am overlooking besides coding 65,535 possibilities?
Solved! Go to Solution.
12-17-2019 10:31 PM - edited 12-17-2019 10:34 PM
When I develop similar application, I don't use case structure.
Your idea is general but as you know, is troublesome. How about following code?
Anyway, in my general step, I place all IO node which would be required. I do an operation of the channels as array operation.
12-17-2019 11:37 PM
That would mean that I would still have to acquire all 16 channels every time. Also, I perform some computations based on the measurements taken, which I need to process in parallel for speed reasons, hence, I do not wish to join the different fixed-point values and then cycle through them all in an array serially.
If a for loop on LabVIEW FPGA doesn't have any iteration-to-iteration dependencies, are all iterations computed at once?
12-18-2019 01:16 AM
In my opinion, placing FPGA AI I/O into case structure lose an outlook of program.
It makes difficult to check source code and if a node is placed in multiple case, it wastes FPGA resource.
If you just want to compute data, I recommend to do the operation in SubVI and use SGL or standardized fixed-data type.
12-18-2019 02:26 AM
I don't have a solution regarding the different fixed-point types (but why/how do you have these - you said two of the same module, no?) but you don't have to acquire all channels - you can (I think) use array subsets.
You cannot allow the references to be dynamic though - so you can't for example specify them from the host PC (again, AFAIK). They must be specified as BD constants (you also can't select by reference, which is annoying but I'm told a necessary requirement, see https://forums.ni.com/t5/LabVIEW-FPGA-Idea-Exchange/Selecting-between-two-I-O-refnums-not-allowed/id...).
If you have a For loop in a SCTL, the loop will be unraveled and all iterations will happen at once. If this can't be done, the compilation will fail. You don't need to add the P node.
Outside of a SCTL, I think it behaves like a normal For loop on e.g. Windows - they will run one after another.
If I set a For loop with "Iteration Parallelism" (i.e. the P node) then I get an error - "For Loop with iteration parallelism is not supported on this target." (cRIO-9045, presumably general?)
This is true both inside and outside of SCTL (so you can never have the P node).
12-18-2019 02:40 AM - edited 12-18-2019 02:42 AM