09-11-2018 04:57 AM
Hello!
I have some doubts about the simultaneous acquisition in LabVIEW FPGA.
Assuming for example that I need to acquire 16 channels simultaneously. Using the 9220 module I can acquire all sixteen channels simultaneously at a speed of 100 kS/s/ch. By using four 9222/9223 is it possible to acquire 16ch at a speed of 500 kS/s/ch, 1 MS/s/ch respectively? Or is there a delay related to the use of 4 different modules?
Thanks,
Regards
Andrea
Solved! Go to Solution.
09-11-2018 05:00 AM
Since the backbone is FPGA, you should not be limited for different card. But you might be limited if in the same card since they use the same connector (I/O)
Benoit
09-11-2018 07:08 AM
Hi Andrea,
I will try to answer your question, so in your example you suggested that you need to acquire 16 channels simultaneously. Let's then look at the modules you referred to.
NI 9220
16 channels, 16-bit resolution, simultaneously sampled i.e. dedicated SAR ADC per channel (SAR = Successive approximation)
16 ch x 2 bytes x 100kS/s/ch = 3.2MB/s of data
What is limiting higher acquisition rates is the ADC itself.
NI 9223
4 channels, 16-bit resolution, simultaneously sampled i.e. dedicated SAR ADC per channel (SAR = Successive approximation)
4 ch x 2 bytes x 1MS/s/ch = 8MB/s of data, so yes, this module produces a hefty amount of data.
If you then would have 4 modules that would correspond to 32MB/s that we need to transfer from the FPGA up to the host through DMA but that should be fine on all newer cRIO controller (Linux based). The bus interface between the FPGA and the CPU depends on the host system, 906x for an example use AXI whereas 903x use a ChInCh interface.
Please look at this white paper, especially section entitled “3. Test 2 - Monitoring Application Throughput Benchmarkâ€
http://www.ni.com/white-paper/52250/en/
Hope this helps!
09-11-2018 07:38 AM
Thanks Jimmie for your kind reply! You have clarified my doubt.
Regards,
Andrea