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Does the Xilinx compiler "learn" from past compilations?

Hi all,


I noticed that if I have piece of FPGA code that is close to meeting timing, after I can get it to compile once, by trying the compile multiple times, it will keep compiling on subsequenct builds as I modify parts of the code not in the path of the code that was causing the violation. 


I also jsut upgraded to LabVIEW FPGA 2014 and the latest xilinx tools (14.7 ISE) from LabVIEW FPGA 2012 and my compiles take way longer and is not meeting timing, on the same code. Is this because I just flushed all the old data from previous compiles?



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Hey qfman,


Every time you compile the resource mapping starts from scratch so I believe this is most likely a "chance" behaviour you are seeing. Between LabVIEW FPGA versions there are different compiling algorithms/overhead which might come into play for the timing or resource allocation during compile. As far as LabVIEW FPGA 2014, are you using your own computer or the Cloud Compile to compile the code? I'd recommend trying the Cloud Compile ( and seeing if you get the same behaviour.


Hope this helps!

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