Does Labview Support a Hierarchical VHDL Instantiation into Labview Clip Nodes?

[EMax]

Hello,

Does Labview Support a Hierarchical VHDL Instantiation into Labview Clip Nodes?

I followed the available help, and called out the top-level VHDL in my XML file.  Unfortunately, my lower level VHDL components are being read as a Black Box and I am getting an error during compile.  So, what must I do to instantiate hierarchical VHDL code into a clip node?

[RyanB]

Yes, but you need to include the paths to all of your VHDL files in your CLIP XML.  This tells LabVIEW which source files to copy into the compilation directory.  Here is an example (which assumes the source files are in the same directory as the XML):

<CLIPDeclaration Name="NI Example CLIP">
  <FormatVersion>1.0</FormatVersion>
  <CLIPVersion>1.0.0</CLIPVersion>
  <HDLName>ExampleClip</HDLName>
  <ImplementationList>
    <Path>ExampleClip.vhd</Path>
    <Path>SubComponent.vhd</Path>
    <Path>Fifo32.ngc</Path>
    <Path>ExampleClip.ucf</Path>
  </ImplementationList>

[EMax · Accepted solution]

Thank You Ryan,

I tried that but still generated an error.  However, I recently found that it will compile my hierarchical code sucessfully only if the name of my Clip Node is the same as my top level VHDL name (In addition to including a path to all of my VHDL components).

[RyanB]

I'm glad you got it working. 

You are correct that the   <HDLName> value must match the entity name of your top level CLIP component.  

[JimmyOC]

This solution should be included in the CLIP tutorials.

I just spent 2 days trying to find out what the problem was until I came across this solution.

I'd like to see this function included in the CXG xml tool also where you simply select all of your vhdl files and its included automatically in the xml output.