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Digital counter is not working when the frequency is higher than around 650 Hz in sbRIO-9637

Hallo Everyone,

I am using sbRIO-9637 for digital data acquisition. I will use a speed sensor around 2 KHz frequency. For testing, I am using Square wave from a Arbitrary Function generator to get the digital input in the hardware. I put a counter to count the rising edge in the FPGA VI. The counter is working fine till 650 Hz. After 650 Hz the counter is not giving any values.

Is there any limit of frequency in the sbRIO-9637? How can I solve this problem?

I have attached a screen shot of the block diagram of the counter.

I am quiet new in LabVIEW. Please let me know how can I solve it.

Thank you.

counter.png

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Hi Legolas,

 

I didn't know that elves are electronics passionates ... 🙂

The Counter implemented on the FPGA looks good, but I would be grateful for sharing the code of the subVI to be sure everything there is fine. The DIO are connected directly to FPGA so there should be no problems with using them in SCTL with 40MHz as you did - if the code compiled without errors it means that it works ... and I don't see any reason to believe that it can be caused by the reader side. 

 

Can you please share more details about the signal generation? How exactly do you connect DO with DI? what is the Voltage level of the generated signal?

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CLA,CTD,CLED
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Hallo MateuszLoska,

Ocuupational hazard for the elves. Smiley Very Happy

I solved the problem just by changing the DIO pin. I connected it with another DIO pin and it was running good for 10 KHz also. May be that DIO pin was somehow damaged or some other thing.

Thank you for your help.

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