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Digital comm on FPGA

I have some hardware with an SSI interface. The data comes in MSB to LSB and is 12 bits. For my own knowledge, is there any benefit to packing the bits in the correct order into a number versus building up a boolean array and reversing it, either in terms of size or efficiency? 




This isn't so much about solving the problem, as I already get the value back from the hardware, but about understanding efficiencies on FPGA


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I suspect that the boolean array is more efficient since both Reverse 1D Array and Boolean Array to Number are "free" (pure wiring) operations on the FPGA that require no clock cycles. The final output from the boolean array to number should be changed to a U16, though. If you want to be sure, compile both versions and compare.


Also, if your numbers are signed, then it's much easier to use the boolean version due to the sign extension option of Boolean Array to Number.

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