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Difficulty clearing Error -61017, "Must recompile FPGA VI for selected target", suspect a bug.

We are developing a stimulator that generates a Pulse Train and simultaneously takes measurements of the waveform (typically 1 ms current pulses at 20 to 200 Hz for a few seconds).  We have SPI A/D chips that take these measurements (typically 10 samples at 10 kHz during each pulse.

 

We are using a myRIO in a LabVIEW RT environment for this Project.  FPGA code in the myRIO generates TTL signals that "power" the stimulus waveform (using DIO lines), and also provide the digital lines to drive the SPI signals for the A/D chips.

 

Thing are "mostly working", but we occasionally add a "flag" in the FPGA so we can monitor (from the RT side of the myRIO) the state of the FPGA (such as the current value of one of its counters).

 

We have been plagued by persistent and difficult-to-banish occurrences of Error -61017 when attempting to start the FPGA code from the RT-Target by executing an Open FPGA VI Reference function with our FPGA routine specified as the VI.  Every so often (more frequently now, like every other day as we tweak and debug the Target and FPGA code to work together).  The explanation for the Error is "Must recompile FPGA VI for selected target", but we just did that!  We do it again, and it still doesn't help.  Running with Highlight Execution shows that the Error arises from Open FPGA VI Reference function, which is the first function we call in the VI we wrote to get the FPGA code up and running.

 

We are developing with LabVIEW 2019, SP1, 32-bit with the myRIO Toolkit, running on a Windows 10 Enterprise PC (we've seen this on several PCs used by the team).  We are using the Xilinx Vivado 2017.2 (64-bit) compiler that comes with this system.

 

We've tried several things, not always successfully, to clear this error.  Deleting the FPGA Bitfile folder and re-compiling didn't help.  I tried specifying the bit-file, rather than the VI (which I should not have to do, it seems to me), but stopped when I noticed the broken Run arrow on my "Start the FPGA" VI.

 

What worked (but was a pain) was to do the following:

  • Copied the FPGA VI and gave it a new name.
  • Create a Build Spec the new FPGA VI.
  • Build it.
  • Attempt to use the new VI (after successful compilation) with Open FPGA VI Reference.  It automatically "pointed" to the old FPGA VI, but I "insisted".
  • That worked!  Inspection of the FPGA Reference wire confirmed that the additional Controls and Indicators I'd added were present, meaning this was the correct code.

A search for Error -61017 on the Web shows several "hits".  A similar search in this LabVIEW Forum shows quite a few more.  My colleagues and I are convinced that this is a "bug" -- at the very least, "the Error Message is Wrong", as we just did "recompile (the) FPGA VI for (the) selected target".

 

Has any CAR been generated for this problem?  Does anyone have any insight into what may be causing this?  In the past two weeks, I've run into this at least 4 times -- while I have managed to get it to "go away", I'm not sure what I did to cause it, and also not sure what I did to "fix" it (the "renaming" trick that worked today was suggested by a senior colleague with more FPGA experience than I who was as puzzled as I was by the problem, but more imaginative in thinking of a "wild idea to try" -- I've since renamed the FPGA file back to its original name, compiled it again, and "all is good").

 

Bob "Puzzled" Schor

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Do you share any VIs between FPGA and other targets?

Do you use conditional disable?

Are you sure that source code separation is active for all VIs?

 

I tend to link to bitfiles instead of linking to VIs. I don't see the benefit, it only brings headaches.

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@Intaris wrote:

Do you share any VIs between FPGA and other targets?

The FPGA was a single VI that was only in the Project under the FPGA section.

Do you use conditional disable?

No.  I have, on occasion, used Diagram Disable with an Enabled and Disabled State when testing, but this had no such structures. 

Are you sure that source code separation is active for all VIs?

Yes.  I checked it before starting to work on the code yesterday (during which time I made several changes to the FPGA, all of which were error-free except for the last, where I added a U16 indicator to let the RT side "see" a variable to verify that the FPGA had run the expected number of times.  I also checked the Project before re-committing it, and everything remained "marked".

 

I tend to link to bitfiles instead of linking to VIs. I don't see the benefit, it only brings headaches.

I assume you mean that using VIs as links only brings headaches.  I can't dispute this, but (a) linking to VIs appears to be the LabVIEW default, (b) it is the "simplest" and gives you the "neatest" appearance on the Block Diagram, and (c) "If It Is Broke, Why Doesn't NI Fix It?"


Thanks for your comments.  I will say that in the months I've been working on this particular Project, it is only recently that I've been seeing these problems (perhaps because my FPGA code has grown a bit, but it still compiles in under 6 minutes and fits, with default Compile options, in my FPGA).  As I noted above, I probably did 6-7 Builds of this FPGA code yesterday after minor edits, and all were problem-free except one.  Furthermore, after this (fixed by renaming the code and trying again), I was successful in renaming it back to the original name and recompiling.

 

Oh, here's a related question.  If I right-click on an FPGA Build Spec, the first two options are "Build" and "Rebuild".  I do not understand the difference (I found a description of this, but still don't quite "get it").  What I want to do is to cause the FPGA code to be given to the Compiler, and a new BitFile constructed, even if there are no change (it is OK if the compiler tells me "There are no changes -- are you sure you want to Compile and Overwrite?").  Should I choose "Build", or "Rebuild"?  Which one corresponds to opening the Build Specification and clicking on the (only) "Build" button?

 

Bob Schor

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