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Different types of memory on FPGA

Hello,

 

I'm trying to understand the difference between the two types of memory on my FPGA. There is Block RAM and DRAM( http://sine.ni.com/ds/app/doc/p/id/ds-366/lang/de ). Is the Block RAM faster to access than the DRAM? How can I specifically access one or the other progmatically?

 

I want to transfer data from my FPGA to my Host, but my  FPGA is to small for the DMA size I want. Would it make sense to first transfer the data to the DRAM and then from there onwards to the Host?

 

 

 

Greetings

 

Matthias

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Hello Matthias

 

To create a target-scoped memory item, which you can access in the entire FPGA VI hierarchy, right-click the FPGA target in the Project Explorer window and select New»Memory from the shortcut menu. The Memory Properties dialog box appears.

This dialog includes the following components:

 

Name—Specifies the name of the memory item that appears in the Project Explorer window

or in the VI-Defined Memory Configuration node. The name also appears in the Memory

Method Node on the block diagram.

 

Requested number of elements—Specifies the number of elements you want to hold in the

memory item. The actual memory usage, in bytes, depends on the number of elements and data

type you specify.

 

Implementation—Specifies how the FPGA stores this memory item. Contains the following options:

 

Block Memory—Stores the data using embedded blocks of memory. Xilinx literature

describes this implementation as block RAM or BRAM. Memory items using embedded

block memory take one clock cycle to execute. Use block memory in the following

situations:

• In a single-cycle Timed Loop, when you do not need to access this memory during the

same cycle as the one in which you give the address.

• When the amount of memory you need is large.

• When you do not have enough free logic resources available on the FPGA.

This option contains the following component:

Actual number of elements—Returns the configured number of elements.

Sometimes the requested number of elements is not compatible with the memory

configuration. In these case, the Actual Number of Elements is coerced to a

compatible number.

 

Look-Up Table—Stores the memory item in look-up tables available on the FPGA. This

storage consumes logic resources that the FPGA uses for other logical operations, such as

addition and subtraction. Xilinx literature describes this implementation as distributed

RAM or LUT RAM. Use look-up tables in the following situations:

• You are accessing this memory in a single-cycle Timed Loop and need to read data from

the memory item during the same cycle as the one in which you give the address.

• The amount of memory you need is smaller than the minimum amount of embedded

block memory on the FPGA.

• You do not have enough free embedded block memory on the FPGA.

This option contains the following component:

Actual number of elements—Returns the configured number of elements.

Sometimes the requested number of elements is not compatible with the memory

configuration. In these case, the Actual Number of Elements is coerced to a

compatible number.

 

DRAM—Stores the memory item in DRAM available on the FPGA. Not all hardware

supports using DRAM for memory. This option contains the following components:

Actual number of elements—Returns the configured number of elements. Sometimes

the requested number of elements is not compatible with the memory configuration. In

these case, the Actual Number of Elements is coerced to a compatible number.

Maximum outstanding requests for data—Specifies the number of maximum

requests for data the application allows to be outstanding.

DRAM bank—Specifies which DRAM bank to use.

Allocated here:—Indicates the amount of memory allocated in this memory item.

Allocated elsewhere:—Indicates how much memory is allocated in other items.

Available:—Indicates how much memory is still available in the bank.

Total physical size:—Indicates the total size of the bank.

 

LabVIEW FPGA Course Manual

© National Instruments | 8-11

 

This is content from LabVIEW FPGA course.

 

Best regards,

Simon Hofmann

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Target-scoped memory items are available within any FPGA VI under the same target in the
Project Explorer window. If you send an FPGA VI with a target-scoped memory item to another
user, you must also send the project. Otherwise, the FPGA VI is broken.

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may google help you more

hi ?Q>

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steinhagelvoll wrote:

I want to transfer data from my FPGA to my Host, but my  FPGA is to small for the DMA size I want. Would it make sense to first transfer the data to the DRAM and then from there onwards to the Host?


How large do you want your DMA FIFO to be? Why do you need one larger than fits on your FPGA? When you create a DMA FIFO, it uses two blocks of memory: a small one on the FPGA, and a much larger one on the host computer.

 

The host computer's CPU periodically copies data from the FPGA memory to the host, or vice versa depending on the DMA direction. Usually this happens fast enough that you won't lose data even with a relatively small buffer on the FPGA.

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To elaborate on what nathand said: http://zone.ni.com/reference/en-XX/help/371599H-01/lvfpgaconcepts/fpga_dma_how_it_works/

The link at the bottom also seems particularly relevant to your question: http://zone.ni.com/reference/en-XX/help/371599H-01/lvfpgaconcepts/fpga_dma_fifo_buffer_size/

Cheers!

TJ G
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