Delay on execution

[OmarIsi]

Hi Lagunasol,

Effectively those are basics examples, the main goal is to learn how can we have principal communications between PC Host-CRio-FPGA.

The recommendation is to have only basic operations in the FPGA, this to ensure the deterministic tasks in the device. In the CRio we can have a more elaborated VI, practically all the applications is in the CRio and the FPGA. The host PC just monitor the shared variables created in the CRio, for visualization or control them.

With an implementation like this we will reduce the communication delays and improve the performance in our application.

When you talk about speed in the CRio, what do you mean? 

The CRio 9074 is a real time controller, you can have a deterministic tasks on it. It has a 400MHz processor. The acquisition rate or output rate depends on the modules we are using. 

For this applications you need signals about 1ms output rate, you can reach this rate with this equipment with the correct configuration.

I'm sharing with you some examples for this kind of communication:

http://www.ni.com/example/26726/en/

https://decibel.ni.com/content/docs/DOC-7702

http://www.ni.com/example/26548/en/

[lagunasol]

I know that the RT cRIO has a 400 Mhz processor, which is more than the FPGA 40Mhz but each time I try to use a code with RT I keep getting the error message "waiting for Real-Time target to respon" and then it stops and disconnects. Thats why I started using FPGA code instead. I don't know why the cRio keeps getting that message even if ,I handle sequence and gave them 1 second delay, scan engine has been set at 10, 100, 1000 ms but keeps having that issue... I have my vi in FPGA and host made it in RT Target. I still dont understand why 😞

[OmarIsi]

Hi Lagunasol,

That error could be caused by a CPU saturation in the CRio, may be caused from polling cycle. This reffers you may need a timed cicle, you can have this just placing a timer loop in the FPGA cycle. Even in the RT CRio you can implement tools for synchronization or timed loops instead. 

I found an example where demonstrate use of Analog inputs and outputs with a FIFO. I think this exameple could helps you in this project. This example is in the example finder installed with LabVIEW, I share to you an image where you can find it.

I supposed you change the code in your project, can you share it with us? 

Regards!

[lagunasol]

I tried to separate the code in different Subvi and make comunication between the FPGA and the RT Target on cRIO, the CPU load problem is kinda fixed but the output pulse waveforms are not working on RT, not sure if I should code it different from the FPGA (in the FPGA I checked difference with tick counters to count miliseconds until I reached the miliseconds when I wanted to make a pulse)

Also, the output signals are better to be on FPGA or in RT?? I know the crio has a speed of 400MHz but the scan engine cannot run that fast right? only at 1kHz or 1MHz and at 1MHz is already saturating the CPU, but when I use FPGA the CPU usually wont get saturated. 

Would it be better if instead of doing 

Read> Detect Zero Cross > count > Pulse > Read >Detect Zero Cross > Count > Pulse > Read... 

I just read everything from the start and calculate an average time for each Zero cross and use that time as a reference? (not even sure if something like that is possible)

Maybe I need to change my code strategy, my main problem wich makes me have comunication between FPGA and RT is that I need to do an Inverse Cosine. 

Here I attach the modified code and vis

[OmarIsi]

Hi lagunasol,

there are some good news!

the output signals should be in FPGA to get the accuracy you want. The max output rate you can reach depends on the CRio you're using, that data is in the user manual. 

the inverse cosine functions is available in the RT so, you can have the maths in the RT and just control I/Os in the FPGA.

Indeed you can do what you mentioned, the get the time in the zero crossing and get an average value to have the calculations. for this you should need to use shift registers.

I tried to open de files but I can't...

Regards!