06-28-2018 10:11 AM
I had implemented the wait inappropriately in my FPGA which I later fixed it. Also I had the coercion dot in my target. It was due to the word length of my FIFO. I later changed it to take care of the dot. But still the output wave was too fast. Now according to your suggestion, I changed the FIFO data type to SGL. Now I almost have the correct wave (Please refer to the attached waveform image). I think it is because I still encounter a FIFO timeout. Should increasing the delay bit more do the trick? I also switched to using waveform graph, which I think might be more convenient for later exporting its data to excel. Please let me know if that is true.
P.S: Please find the attached project, host and target VIs for reference
06-28-2018 10:51 AM
1. Your Count(uSec) on the FPGA is defaulting to 0 and I don't see anywhere that you are changing that value. Change it to a constant and make it 10uS to give you a sample rate of 100kS/s.
2. Your FIFO size is too small. Increase it to be 2047 elements. This will give you a buffer size a little more than 2 full reads of the host. You should change this value on the Host VI as well.
06-28-2018 12:54 PM
I set the count on FPGA to a constant. I also increased the FIFO size to 2047 on both sides. But still the FIFO timeout indicator glows as soon as I start the execution. It means that I am loosing data, right? But the wave appears to be continuous and has some DC offset (I expect 1Khz 2Vpp sine wave). Also I noticed that when I changed the data type of FIFO to SGL, a coercion dot appears after the FPGA I/O node in FPGA VI. Is this causing the offset?
Please find the attached VIs and waveform image.
Thanks a lot!!