Daqmx External clock for PXIe-4357 RTD module

[London]

Hi,

I am using PXIe-6358 & PXIe-4303 Analog input cards and PXIe 4357 RTD card on PXIe1082 chassis. 

My goal is to synchronise all 3 cards and acquire data at rising edge of an external clock.

I managed to synchronise them by having a common reference clock (PXI_CLK10) and common start trigger. Then I fed a sine wave to a channel on each card and managed to acquire that sine waves and verified that they are in sync. However, sample clocks are still taken from on-board clocks (i.e. source terminal of Sample Clock VI left default). 

I am generating a 1kHz continuous pulse train at PXIe-6358 counter 0 and I need to use this as sample clock for above 3 cards. From my understanding, I can route this to PXI_Trig0 and use that to source terminal of sample clock vi of each task. However, I have following issues.

1. PXIe-4303 complaints that it is not supported. According to the manual, it only accepts reference clock and start trigger as sources!

2. PXIe4357 RTD module can only acquire data at 100Hz. It throws an error when i try to oversample. Therefore, my end goal of having a 2D array of 1000x3 elements (1 sample at 1KHz from a channel from each card) is not possible.

Really appreciate of someone can give some tips if there is a way I can achieve my task.

[Riley_Ilieva]

Hi, 

1. The PXIe-4303 card has filter delay enabled by default that could potentially be causing the problem. You can see what that is set to on page 6 of the manual -http://www.ni.com/pdf/manuals/377007b.pdf .  You can remove it by changing the AI.RemoveFilterDelay attribute/property  - https://zone.ni.com/reference/en-XX/help/370466AC-01/mxdevconsid/filterdelayremoval/ . Alternatively, if you acquire data from all cards under the same task, they should synchronize.

2. What you are trying to do is beyond the physical limitations of your hardware. The only workaround I could think of is to write the same measurement 10 times but you mentioned that you get an error when you oversample. What is the error and how are you trying to go about oversampling? Could you attach a screenshot of the part of the code where you do that?

Many Thanks, 

Riley Ilieva

Applications Engineer

National Instruments

[London]

Hi,

many thanks for looking in to my query. I have been struggling with it for nearly a week and really appreciate your support.

1. There is a property available under timing property, Sample clock -> Digital filer -> Enable. I tried to write False to it but there is an error. It seems 4303 cannot accept an external clock.

2. please check the VI snippet. This is all working as expected. Where I am struggling is, to route the pulse train (at counter 0, PFI 12) to sample clock of each card. So that as I vary frequency of the counter, I could obtain variable sample frequency.

[Riley_Ilieva]

Hi, 

No worries, we are here to help. 

I am afraid that the resolution of the screenshot is not good enough so I cannot read the text on it and it is difficult to be able to understand what you are referring to. Could you send it as a VI rather than a screenshot? Could you also tell me what the error messages you are receiving are and at what point of running the code they appear? 

Is there any particular reason why want to use a timing signal from one of the cards in particular? If you know the sample rate, can you not set that in the sample clock? 

Also, there is an example if you go to Help>Find Examples> Directory Structure>DAQmx>Synchronization>SubVIs>Analog Input - Voltage and Thermocouple in a Single Task.vi . The data you are reading do not need to be of the same type, you can call DAQmx more than once. That should give you an idea of how you can set these up in a single task and would make it easier for your data acquisition to be synchronised. 

Many Thanks, 

Riley

[London]

Hi,

Apologies, I thought I have uploaded the VI snippet but it seems, it has taken as a picture!.

By further looking in to PXI4303 manual, apparently it doesn't except an external clock. That's why it has been giving errors. So I have to think of another way to do this.

Please see attached VI. Basically, I am generating a pulse train on counter 0 and I could vary the frequency at run time. Then, I need to take one sample from 4 analog input cards at falling edge of each pulse generated at counter 0 (PFI 12).

Initially, I thought of routing PFI 12 and use as en external sample clock for each card but now I understand that's not possible.

Please let me know if there another method.

Also, please note that, I vary frequency of the pulse train from 2kHz to 50kHz. Out of the 4 cards, 3 of them can sample upto 50kHz but PXIe 4357 RTD module can only do 100Hz. So I have to duplicate samples as well.

Really appreciate if you can advise.

[Kevin_Price]

Sorry, not at a LV machine and can't look at your code now.

I'm usually an advocate for simpler sync schemes, often based solely on sharing a sample clock and not even setting up triggering.  This can work fine for many common "regular" MIO and similar boards.  It won't work for you.

Speaking very generally, to keep all your data correlated requires both:

1. all sample timing is referenced from a single master timebase source

2. relative times of first samples are controlled or known.

Your specialty temperature won't accept an external sample clock and you plan to acquire other data at a variable rate.  So your issue is trickier than most.

I'm not an expert on the PXIe platform, but I *think* that most boards either will or at least *can* lock onto the backplane reference clock.  I think it was 10 MHz on PXI systems, not sure what it is on PXIe systems.  Whatever, you'll need to get all boards locked onto that single master timebase.  (This might actually happen by default.) 

Then all that's left is to use triggering to control the start times.  If somehow the triggering options aren't sufficient, you can probably do something with a counter to measure a time offset between temperature sampling and regular AI sampling.  Even though the temperature board won't accept an external sample clock, it'll probably be able to export its sample clock signal for other boards to see.

-Kevin P

[Riley_Ilieva · Accepted solution]

Hi, 

Thank you for sending the VI.

There is some information on reference clock synchronization on page 2-17 of the PXIe-4303 manual - http://www.ni.com/pdf/manuals/377003a.pdf . Is that what you have based the VI timing on? There are some tips and directions on there. 

We have a white paper on different timing and synchronisation options here - http://www.ni.com/white-paper/11369/en/ that has a lot of information. Does any of this give you any ideas of how you could set it up? There is some more info here too - http://zone.ni.com/reference/en-XX/help/370466Y-01/mxcncpts/syncrefclock/ . 

Have you thought about using the DAQmx trigger function? 

Many Thanks, 

Riley Ilieva

Applications Engineer

National Instruments

[London]

Hi,

Thanks for all tips.

Apparently, apart from PXIe 6358 all other PXIe cards only accept an external clock for Start trigger and reference.

So, according to the manual I can't achieve my goal.

Hence, the solution is to sample at 50kHz (which is common to all cards) with PXI_CLK100 reference clock and a common start trigger. Then extract necessary data points.