DRAM performance on flexrio 7965R

[irad]

Hello,

I am working with flexrio 7965R and I would like to get more information on the performance of its DRAM memory. The only parameter that the datasheet gives is the maximum theoretical data rate which is 1.6 GB/s. In particular I am  interested in the DRAM control signals and its performance when it is configured as 128 bit FIFO with the clip node.

1) Performace

I tried writing continously to DRAM (configured as FIFO) in a 100 Mhz single cycle timed loop. This pushes the data rate to 100 x 16 bytes = 1.6 GB/sec. This didn't work so well because it was obvious that some data was lost. This wasn't surprising because the data rate was at the limit. On the other hand, the reading speed seemed a bit slow. In the 100 Mhz single cycled timed loop I tried reading data on every fourth clock cycle without writing at the same time. There are no problems during the first 30000 reads or so but then the DRAM starts to break down. It starts outputting incorrect data although it recovers later.

Does 1.6 GB/sec applies to reading or writing speed? What if reading and writing are done at the same time? What would would be the aggregate rate in that case?

2) Control signlals when DRAM is configured as FIFO

I know that DRAM is not always able to respond to read or write requests because of its non-deterministic behavior. In the FIFO mode how can I ensure that DRAM  is always ready for writing and reading before these actions are requested? The only two signals I can see are Full and Data_available. Is Full only asserted when the FIFO 

is full or any time the DRAM is not ready to receive data? Similarly, is Data_available only asserted when the FIFO is empty or any time the DRAM is not able to output data?

When I was reading data from the DRAM  in 100 Mhz single cycle timed loop on every fourth cycle I monitored Data_available signal. It was always high. But the data

was still not correct all the time.

Regards,

Ivan

[Ben_S]

irad,

Hello! First of all, I reccomend you check out the LabVIEW Help file titled, "FIFO - 128 Bit Memory Interface".

1) Performace:

Does 1.6 GB/sec applies to reading or writing speed? What if reading and writing are done at the same time? What would would be the aggregate rate in that case?

The 1.6 GB/sec applies to both reading and writing speed as there is actually only one read/write line that goes from the FPGA to the DRAM on the FlexRIO. If you told it to do a read and a write at the same time, it would still be 1.6GB/sec because the DRAM is DDR memory which means it is able to do read/write operations on both the rising and falling edges of it's clock.

2) Control signlals when DRAM is configured as FIFO:

Is Full only asserted when the FIFO is full or any time the DRAM is not ready to receive data?

Is Data_available only asserted when the FIFO is empty or any time the DRAM is not able to output data?

From the LabVIEW Help file previously mentioned, "The FIFO - 128 Bit memory interface is designed to simultaneously read and write data at speeds up to 40 MHz. It is possible to run the interface up to 200 MHz. However, at speeds greater than 40 MHz, the Full and Data_Available signals may temporarily become TRUE and FALSE, respectively." This happens because the DRAM FIFO project element was designed to run at 40MHz and has some background code called the Arbitrator that handles the organization of code going to and from the DRAM chip itself. When you run it faster than 40MHz it can give you "incorrect" status information for the 'Full' and 'Data_Available' status while the Arbitrator is making sure that it most effeciently gets data to the DRAM and back.

How can I ensure that DRAM  is always ready for writing and reading before these actions are requested?

There are multiple options for doing this. One option would be to run the DRAM FIFO at 40MHz and write multiple samples to it with eatch iteration of the loop allowing you to get the same throughput (1.6GB/s) and have accurate status information.

Another Option is to use the Random Access DRAM instead of the DRAM FIFO and configure your own aribration code that doesn't have the same limitations as the built in DRAM FIFO's Aribrator.

For more information, check out this link: http://decibel.ni.com/content/message/4427#4427