DMA host to FPGA array size

[jyang72211]

Currently, I am sending 3 clusters with 11 element each to the FPGA (PXi-7833R).  I thought perhaps, it will be more resource efficient if I were to send the data to the FPGA through a DMA instead.  Is that the case?  

When the data arrives at the FPGA, I use a for loop to read all 33 elements into an array, and use the array to build the original 3 clusters within the FPGA.  By doing that, I eliminate the 3 clusters of the FPGA front panel.  On the FPGA side, I dequeue the 33 elements from the DMA with a for loop, but LabVIEW is telling that that array is not a fixed size.  Is there a way around this?

[crossrulz]

How often are you updating these clusters?  If not very often, then just put the clusters on the front panel of your FPGA and write directly through them using the FPGA interface.  It will be less of a hack.

[nathand]

Can you post your code? That would make it much easier to understand where the undefined-size array is. I can't think of any reason this wouldn't work, so I suspect that it's simply a programming error, and a not a fundamental problem with the approach. That said, I don't know if you'll save resources - you might just be trading some resources for others. The FIFO will occupy a block of memory and there will be some logic needed to decimate it. If your clusters are all have the same number and type of elements (ie, could be wired to each other), and you don't need the high throughput of the FIFO, you could also do this with a single cluster control, a boolean (or interrupt) for handshaking, and maybe an index as to which cluster is updated if you don't always want to do them in sequential order.

[jyang72211]

I already have cluster on the FPGA front panel for data transfer.  I am trying to explore other way to see would resource utilization goes down.

[nathand]

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@jyang72211 wrote:

I already have cluster on the FPGA front panel for data transfer.  I am trying to explore other way to see would resource utilization goes down.

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I may have misunderstood your original post. I thought you meant that you currently have 3 cluster controls on the front panel, and I was suggesting you could replace them with a single cluster, but maybe that's what you already have.

[jyang72211]

Actually, I do have 3 cluster on front panels now.  Would using one cluster be a lot better?

[nathand]

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@jyang72211 wrote:

Actually, I do have 3 cluster on front panels now.  Would using one cluster be a lot better?

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No, but it might be a little bit better, depending on the number and type of elements in the cluster.

[Dragis]

I think this gets back to the request for more information about your application. What are those 3 clusters used for? How often do they get updated? Do they always have similar element values or are they completely different? Do you need to read the values back from the FPGA? Things like that would help design things correctly.

[jyang72211]

The clusters are used to passed data from host to FPGA.  They get updated once every minute or more.  Before the clusters are updated, a false case in a while loop is executed.  The false contains little code.   After the clusters are populated, a true case of the while loop is executed, which contains code for waveform injection.  The elements in the clusters are all numeric of different type.  These clusters are only from host to FPGA.  

[jyang72211]

I tried to repeat the problem, but I can't.  I will look deep into this and post an example.