DMA Host Transfer of 80bit with a Fifo in an SCTL

[westgate]

Hello,

im Running an SCTL on my FPGA. In this SCTL i read 10 times 8bits that have to be transferd to my Host system via DMA Fifo.

If i would have 64 bit instead of 80 bit i simply would use the Join Numbers Function and use a U64 Fifo.

So what can i do?

Is it possible to create a 80bit Datatype?

Or can i input 2 Values into a Fifo in an SCTL some how?

Thank you for your help

westgate

[Spectre_Dave]

I would accumulate the bits on a shift register until you reach a block (64 bits) or the end of the data.  I would then transfer each block (64 bits) via DMA to the Host.  i do this all of the time. See See my 1-Wire sample code

Message Edited by VADave on 04-28-2010 12:04 PM

[westgate]

Hello,

well my application is time criticall.

I would like to output all 80bit at once every SCTL loop iteration.

So your solution is good but maybe not the right for me.

Thanks

westgate

Message Edited by westgate on 04-29-2010 05:14 AM

[Spectre_Dave]

You could write to a FIFO within the SCTL and read the FIFO and use a DMA to move the data to the host. 

Since 64 bits is the most can move at a time I would transfer 40 bits on each DMA transfer and put the data back together at the Host.