LabVIEW

cancel
Showing results for 
Search instead for 
Did you mean: 

DMA FIFO start

Highlighted

hola everybody

 

i know that there are other messages about this topic but i didn't find what i want, so here is my problem : i'm using a DMA FIFO target to host and normaly when i execute the host VI, the FPGA VI should atomatically execute himself too, but it doesn't work, and when i try to stop my FPGA VI it doesn't stop 😕

 

attached, some picture to show you my program and my setting ( nothning change if i check "dinamic mode" or not 😕 )

 

thanks !

Download All
0 Kudos
Message 1 of 5
(1,162 Views)
Highlighted

Generally you should not open and close the FPGA reference in a loop; instead, open the reference once before the loop starts, and close it after the loop stops.

 

You might be confusing starting and stopping the FPGA, versus starting and stopping the DMA FIFO. Your code shows that you start and stop the FIFO. The FPGA will keep running after you close the reference. Can you be more clear about exactly what is not working, and what you want it to do?

0 Kudos
Message 2 of 5
(1,125 Views)
Highlighted

hi !

 

Thank you for your answer nathand. i did some changes on my host VI as you told me (see attached). so, to be more clear : when I start  the Host VI, the target VI doesn't launch himself. But he should, right ? so, that is the first thing who desn't work.

secondly, when i clic on the stop button of the host VI, the VI doesn't stop and continue to run Smiley Frustrated and i don't know why Smiley Sad

 

 

0 Kudos
Message 3 of 5
(1,097 Views)
Highlighted

sorry i attached the wrong picture, the new one is the lastest one

0 Kudos
Message 4 of 5
(1,093 Views)
Highlighted

How do you know the FPGA VI is not running? Is it possible that the FPGA VI does run, but only once (for example, if the default value for the FPGA's Stop button is true)? If the FPGA VI does not run (or doesn't run continuously), then your host VI won't stop when you click the front panel Stop button, because it is waiting forever for data on the DMA FIFO that never arrives.

 

It might also be helpful to wire the error terminals, so you can see if some error is occurring on one of the FPGA nodes.

0 Kudos
Message 5 of 5
(1,073 Views)