DMA Data Acquisition with FIFO

[soljiang]

Hi, all,

I'd like to ask a favor to get some help understand FIFO.  I attached the files here and it simply the most basic FIFO target to Host data tranfer.  I set the Requested number of elements to 4095, which I understand to be the depth of FIFO on FPGA.  The sampling rate on FPGA is 10KHz.  The loop rate on Host of reading is 10ms.  The depth in Host FIFO.configure is 10000, which I think is the number of elements in the host memory part of the DMA FIFO.  So I guess the total depth of FIFO is 14095 elements.  I set the points of reading in each iteration to be 2000 points.  However no matter how I change the combination, and number of points to read, the program runs one iteration and then shows a different error message.  

Can someone please help me understand how to calculate each parameter and optimize it, if the sample rate I want on FPGA is 10KHz I16 integer data?  Thank you very much.  I appreciate your help!

Best,

Charles

I attached all the files here, which is very similar to the example on ni.com

[smithd]

Hi Charles,

What example are you referring to on ni.com? What error messages are you getting? Are these errors being returned by the windows VI or by the FPGA VI?

Looking at your code, there are a few possibilities I can think of:

-Are you sure that the windows VI is actually executing at 10 ms? Can you use tick count VIs and sequence structures to be sure? If the windows VI is taking longer than expected, the fifo may be filling up.

-Are you configuring the depth to 10,000 before you start the VI? It looks like the default is 0, so if you forget to enter the right value, you may run into a problem there.

-You may consider setting the timeout on the fpga VI to -1 so that it will not try to write to a full fifo.You might also do this on the RT VI, so it waits permanently for data.

-You should explicitly convert the count (usec) value from a double into a U32 and use a probe to confirm that this count is what you expect. Alternatively, simply use your control to modify that value directly, without any of the dbl division you have now.

-You have the timeout on your FIFO set to 10 times the desired loop rate (windows VI). What is possibly happening is that your FPGA VI is not given enough time to fill the buffer before the windows VI times out the first time. I would set that timeout to -1 so it waits for data, at least on the first run of the loop (using the 'first call?' VI).

Let me know how that works out for you. As far as the numbers you listed, I think everything should be working. However, if you look at some of the examples in the example finder, they use things like interrupts to control the flow of the application and set the timing up correctly.

Thanks,

[soljiang]

Hi, Smith,

Thank you for your response.  Could you offer me more information on the following points:

When you said "You might also do this on the RT VI, so it waits permanently for data."  Which vi are you referring to and is it compatible with FPGA?  In which vi, FPGA/Host should I call this vi?  Also regarding "setting the timeout on the fpga VI to -1", could you please tell me how to execute this?

When you say "explicitly convert the count (usec) value from a double into a U32", do you mean use a data type conversion node in between?

Thank you very much!  I appreciate your help.

Best,

Charles

[smithd · Accepted solution]

Hey Charles,

With regards to the second question, that is what I meant. I am not 100% sure how the coersion dot converts a dbl into an unsigned int, so it would be good to use a conversion node and probe that value, to make sure you are getting the value you expect.

As to the second question, I was saying that you should wire in a -1 contstant into the timeout field of your fifo read method on both the RT VI and the FPGA VI.

Thanks,