Ok. I understand now. I have split the DRDY pin from the digital sensor and fed back to the 8452 and one branch to the PFI0 connection on the 9205. The cDaq 9172 manual (pg. 36 and 37) states that I need to use the di/SampleClock with the PFI terminal to use as a sample clock. However, page 36 also talks about having to route the external signal to an internal one which I am confused about how to do in labview. I've tried giving the source of the sample clock as the PFI0 terminal of the 9205 but end up with an error. So I'm thinking there is something a bit more complicated I need to do to set up the clock on the 9172.
It sounds like your question is just how to configure a DI/PFI as the clock source in a cDAQ
I would recommend checking out these articles.
Synchronizing Multiple USB DAQ Devices
Scroll down to: Multi-device synchronization
Is this example helpful?
This refers to different hardware, but also includes instructions on how to route external digital input as a clock source:
Those examples helped but I still have a question. Both examples seem to indicate that a minimum of 2 PFI lines need to be available, 1 to route the clock signal and 1 to be the start trigger. I believe my hardware configuration only has 1 PFI line on the 9205 module. Would there be any other way to pass the start trigger to the cDAQ?
I have attached a schematic focusing on the wiring for the timing and also my timing node for the cDAQ in labview.
Thanks for the carefully illustrated schematic, that helped a lot.
In order to synchronize your devices, you will need two PFI lines, so the 9205 module will not be enough. You will need a different module in your cDAQ chassis, one with at least two DIO lines. Then you will be able to trigger the sample clock on the cDAQ and share it between the other modules and send it out digitally through the other PFI port to the 8452.
Thank you for the confirmation Joey. I will look into acquiring a 9401 to place into slot 5 or 6. I saw in the 9401 manual that you can hook an SPI device up to that as well. Do you think it would be easier to use the 9401 to have synchronized timing as opposed to the 8452 since that will keep all sensors connected to the 9172 chassis? My only concern is the fact that the digital sensor has its own internal clock to get the sample rate.
I don't believe the Sample Clock DIO pin from the DAQ chassis needs to be connected to the Accelerometer, but rather just the DRDY pin of the 845x to better synchronize. The schematics that you attached are very helpful in seeing exactly how things are connected, however! Also, are you exporting the sample clock on a specific line that is being fed into the DRDY input of the 845x? Also, I don't believe the 9401 in a cDAQ chassis has the ability to perform SPI communication; that would require a cRIO and programming of an FPGA.
To answer your question, I am not exporting the sample clock from the cDAQ. I don't need any particulars of the cDAQ clock to come out, I need to feed it.
Currently, I have both the DIO1 line on the 8452 and the PFI0 line on the 9205 wired to the DRDY of the accelerometer (in this case DRDY is routed to the INT1 pin). I was trying to have the accelerometer sampling rate (which is internal to the accelerometer) drive both the 8452 and the cDAQ chassis which is why I have the wiring the way I do.
Unless the timing parameters for the SPI stream are set up exactly correct, there is no way I can read the accel data using the SPI stream with FIFO without eventually having buffer overruns or underrruns because the clock will be either too slow or too fast. So with the accelerometer DRDY signal hooked to the 8452 DIO1 pin, I am able to read accelerations ONLY when new data is available because the SPI stream waits for the DRDY signal.
I believe the digital accelerometer needs to drive everything since it has an internal clock for data population which is set through control registers. The exact timing is unknonwn because it does not output timing information (i.e. I set 5 kHz but it might actually be 5.01 kHz). The only way timing is known is through the DRDY output on the accel. Since this is a pulse (zero voltage with momentary high voltage when data is ready...aka active high), I was hoping that pulse could be the clock for the cDAQ. This lead me to the wiring configuration which is displayed in the schematic. As Joey mentioned, it looks like that approach could accomplish what I need provided I have 2 PFI lines (currently only have 1).
I understand, I was thinking to have it wired the other way around and have the cDAQ trigger the 845x but it looks like you can possibly use that pulse for the clock of the cDAQ as Joey mentioned.
I am trying to communicate between NI USB 8452 SPI with Slave sensor having ST Controller.i am sending 11 byte data but i am not getting proper response. FF FF up to 11 byte response comming.i am using spi streaming VI . Pls help me out to solve this problem.
Could you maybe elaborate more on you issue? Is it pretty similar to lgbav8r's issue? If so have you tried any of the steps earlier in the forum and what are the results? Otherwise if the details are different I would suggest possibly making a new topic where you can lay out the specifics.
Some things that I would elaborate on are what excatly your code looks like by posting it and possibly the front panel where you can reporduce these results.