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Compiling or Synthesizing HDL code partially

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Hi,

I have a VHDL code which I am integrating in my VI using IP integration node. I want to see that when I will be compiling my overall VI, whether LabVIEW Xilinx compiler will accept this code or not. So, is there any option through which I may compile my HDL code first/quickly  just see whether ultimately that will be accepted or not. 

 

Background: Actually every compilation of the complete module takes almost 45 minute, just to tell me that there is some issue in my HDL code. So, just to save time, I need to compile my design faster/ or at least my HDL code, just to see whether it will pass or fail eventually.

 

Thanks for help

Cheers

TahiR 

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Hello!

To compile your design faster have you tried this LABView FPGA compile cloud service? http://www.ni.com/white-paper/52328/en/

I hope it helps!

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