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Compiling For Loops in SCTL

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I have a large FlexRIO FPGA application that requires the mapping of different input sources running at 200MHz. Originally, we had some code that performed input mapping, but it was code that had been manually parallelized (making it pretty complex) and only had two different possible sources. I had to add a third possible source to our code. Thinking that my understanding of For Loops within SCTL loops was correct, I changed the design to a For Loop implementation (attached).

 

My understanding is that a For Loop of fixed size within an SCTL would be unrolled by the compiler (barring any unsupported features like coercion dots or unsupported structures). With the design attached, my compilation is successful. However, when I add this loop to the rest of my code (replace a couple of the controls with register items), I seem to encounter Timing Violations  from non-diagram components. Because the max fanout values are pretty high when the compile fails, I suspect that fanout is the cause of the failure.

 

I've tried a few different steps to try and get my design to compile (including trying to manually parallelize the For Loop into 4 loops, each auto-indexing 8-element arrays and adding a pipelined stage prior to concatenating the result). Does anyone have any other suggestions or tips?

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Nadine H.
Certified LabVIEW Developer | Certified TestStand Developer
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You should avoid using arrays on the front panel of the top level vi. Especially if those contorls and indicators reside inside of a SCTL running at 200 MHz.

 

If you need to push an array of elements down to the fpga use a host to target fifo. If you continue to have trouble pushing data into the 200MHz SCTL from the host, push the data into a slower clock domain, then use a target scoped fifo to move it into the faster clock domain.

 

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Hey David,

 

Thanks for the advice; I appreciate the help. However, I just posted that VI as an example. In our actual design, the controls and indicators are replaced with Register items for target-scoped tag communication and one Array Control (i know, not ideal) for Host-Target tag communication. This configuration worked fine prior to my making the changes w.r.t. the For Loop functionality.

 

Would you happen to have any other tips/suggestions?

________________________________
Nadine H.
Certified LabVIEW Developer | Certified TestStand Developer
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Unfortunately it's probably the Index Array that's killing you here. From the help:

NotesFor large arrays, the Index Array function might not be able to execute within a single clock cycle, resulting in a compile-time error.
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Hey nathand,

The arrays were indexed in the original configuration without the For Loop as well, so I didn't suspect that would be an issue here. Is a 32-element array considered large enough to cause these issues?

 

To give you an idea, the original configuration (that compiled successfully with the entire code) looked something like the one attached. The subVI was inside an SCTL running at 200MHz. You can probably understand why I wanted to change the implementation to a For Loop.

________________________________
Nadine H.
Certified LabVIEW Developer | Certified TestStand Developer
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What version of LabVIEW are you using? The fpga module ships with the IP Builder in 2015 and later. It does things like for-loop unrolling. I tested it in LV2016 on the for loop vi you posted and it was able to compile at rates up to 250MHz.

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Thanks David. I did try it with the IP Builder but I'm not too familiar with it and I just suspected that the SCTL with LabVIEW FPGA handled that type of optimization for me. Is this not the case?

 

Based on your response, is your recommendation to use the IP Builder instead of relying on the LabVIEW FPGA SCTL optimizations?

 

One thing I noticed with the IP Builder were the min and max Latency values (which were fairly high). I read the Help on this, but I'm still a little confused as to what these values represented. Any insight?

________________________________
Nadine H.
Certified LabVIEW Developer | Certified TestStand Developer
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Sorry, I totally ignored your question! I'm using LabVIEW 2015.

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Nadine H.
Certified LabVIEW Developer | Certified TestStand Developer
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One thing I notice is that in the original (non-loop) version, the "data source" input (which becomes the array index) is an I8, whereas in your loop version it's an I32. Try changing it to an I8 in your version. Even though LabVIEW expects it to be an I32, on FPGA it is quite possible that the compiler can improve the timing when that input has a smaller width.

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Hi nathand,

Nice observation and I completely agree. I actually had to change that to an I32 because there's a bug where For Loops within SCTLs do not allow coercion. Since the index Array function requires an I32, I had to convert my I8 input to an I32. In my complete version, the coercion takes place right outside of the For Loop.

 

Thanks for looking into this!  I'm glad I'm not doing anything glaringly wrong.

________________________________
Nadine H.
Certified LabVIEW Developer | Certified TestStand Developer
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