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Communication between FPGA and HOST

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I'm trying for a week to have a nice communication with my HOST and FPGA.
But it seems that I'm loosing points when I read my fifo in HOST.

Someone has another solution or tell me what I'm doing wrong in my VI's

Thanks a lot

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Message 1 of 8

Do you lose points from the start or only after a certain time?
Please try the case structure as you could see in my attached picture.

Tim Remus
National Instruments
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Message 2 of 8

Thanks a lot for your answer


I change a little bit my program because one of the problem was the flush of the queue.

The signal, in Host, has a better behavior but he continues to loose points (image in attach).


I tried your proposition, but the beahvior is the same

This time, I've attach my project

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Message 3 of 8

I have looked at your project more closely. I've noticed that you're making a lot of mistakes in type conversions. So you generate the queue with fxp <+-,26,5> from the invoke method comes data with fxp <+-,32,10>. And in your FPGA VI you use fxp <+-,24,5>.

Then in your second while loop you convert data from fxp into double and then you use again fxp with the insert into array function. Keep your data types consistent. Use either a double array or leave the conversion see image1 (see comments).

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Message 4 of 8

Yeahh, I've a good signal now. Not perfect but much better.
So like you said I eliminate all the conversion (Red Dots).
But I continue to have one in FPGA, in the wirte into FIFO Block. This one I can't eliminate.

In this project I need to find the fundamental frequency value of a signal.
My input signal come from a frequency generator.

Have you another suggestion for a better transmission between HOST and FPGA? (updated project in attach)

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Message 5 of 8

You can change the setting of the datatype by right-clicking on the FIFO in your project structure under properties.

Otherwise the FIFO is the right choice for your project. See the following link.

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Message 6 of 8

Thanks for all of your answers and sorry for the late reply...

The project works better but not good as I want.

The problem continues to be the transfer between the HOST and FPGA.
The FIFO seems to lose some points in this communciation, and I don't know why does it happen.
This time, I saved in the project  a concatenating graph where we can see a jump between points when I'm reading the FIFO in HOST.

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Message 7 of 8
Accepted by topic author michael86

Ok, so I think i found the solution.

Is the relation with the size of the FIFO of the fpga and the FIFO depth in the HOST.

So, I just define a higher number for the depth (100000) in host and that work fine now.

Thank you very much  for your help

Message 8 of 8