Cluster coercion for FPGA references

[adams156]

I have a cluster of clusters.  One of the inner clusters grew from 25 to 29 elements, but I forgot to update several of my subVI's to reflect.  I seem to remember previously when I did this, I got a broken line and non executable VI, but now it results in a coercion.  Can you really coerce a cluster with more elements into a cluster with fewer elements?  My outer cluster consists of a couple of FPGA references that have register clusters. 

[Dragis]

You are correct that two clusters must have the same number of elements and their elements must each in pair be coercible for a coercion dot. Otherwise the wire should break. If you can upload a simple example showing the invalid coercion that would be helpful.

[adams156]

Unfortunately I had already corrected the coercion that I was having by the time I posted this, but if it happens again, I will be sure to post a screenshot of it happening.  It's a little bit time consuming to reproduce though, just because of  the compilation time on the FPGA.  Thank you for the response though.

[adams156]

I just had the problem pop up again.  I've attached a couple of screenshots.  In the first, you can see the VI that I'm getting the coercion in, and the second screenshot shows a comparison of the two clusters.  The clusters were large,  so you can only see about half of what's in there, but the included half shows where the problem occurs.  The the reference called "FPGA 2 Reference" is supposed to match up to "FPGA VI Reference Out".  Directly underneath each of those references are the register clusters.  One register has 9 elements while the other has only 8.  I feel like this should cause a break.

[JoeySpinella · Accepted solution]

Hi Adams,

FPGA Reference Out is of the special data type "FPGA Reference Dynamic", which dynamically includes a cluster of the Registers, Elements, and FIFO's associated with the referenced FPGA personality. Dynamic data types don't follow the same rules of coercion that we would expect a statically defined data type to follow. The dynamic nature of FPGA Reference wires allow us to wire any FPGA Reference into the input of any read/write control, regardless of if the read/write control was created explicility for the FPGA Reference. This makes programming in FPGA much more convenient.

[Dragis]

Just to extend on what Joey said ... The FPGA references show their context help similar to a cluster, but they aren't clusters. Rather, the view is trying to show the configuration of the reference. When you see a coercion of a reference, it means the references you are passing in has more functionality than what the function needs but it is still compatible.