Clearing Target to Host DMA FIFO

[hussam95]

I am gathering information from FPGA, and sending to host via FIFO. My application requires sending data to host every 'For Loop Iteration' and building a 2D array where every data stream from one iteration makes up a sub 1D array. My question is how can I clear my FIFO after every iteration so I don't overflood the FIFO? 

I am using an NI 7856R Module. 

[wiebe@CARYA]

You typically read from a FIFO to clear it's data. If you clear it at the writer's site, how can the reader depend on that FIFO's data?

It seems to me the FIFO might not be the right model. If you just want to get the nr. of upgoing pulses, an reading "edges" on the host would do.