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Changing GAIN on NI 5734 ADC introduces noise ripples

Hey Nathan,

 

Thank you very much for your thorough analysis of our problem!

 

Since you were mentioning that our problem looks like a timing issue between the FPGA and the FAM I double checked all clocks in my project.

I found that I've somehow set the 'IO module clock 0' of the ADC to 80 MHz, whereas the derived clock I used to acquire samples ran at 50 MHz. Even though I did not use the IO module clock for anything I changed it to 50 MHz to match the clock on the acquiring SCTL. But so far I am experiencing the same problem. I'll try to play some more with the clocks and let you now as soon as I now more

 

Bjorn

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Message 21 of 27
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How are you changing your sample clock rate?  My understanding is that you are using the internal oscillator for the sample rate, and not an external source.  When using the internal sample clock, you can't change the sample rate in the FAM, and the SCTL that you read your Channel data in (AI0, AI1, etc.) must use the "IO Module Clock 0" clock as its source.  

Product Support Engineer
National Instruments
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Message 22 of 27
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Ok then there is one mistake I made so far. I used a derived clock from the FPGA '40MHz Onboard clock' set to 50 MHz as a source for the SCTL. I checked that the acquisition timing is correct using a waveform generator and the time between two samples was 20 ns as expected.

 

Now I recompiled the FPGA module setting "IO Module Clock 0" to "Compile for single frequency" at 50 MHz and use it as the source of my SCTL.

So far it looks like the noise has disappeared. Yet I now experience that my DMA FIFOs are timing out even though I have not changed anything but the SCTL clock. I'll have to look into this matter before I can say anything else.

Thanks again for pointing out what I've done wrong!

 

Cheers,

Bjorn

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Message 23 of 27
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Changing the rate in the IO Mod Clock 0 properies doesn't actually change the Sample rate the digitizer runs at.  Since you are using the 5734, the ADC's are always returning the data at 120MHz.  You can decimate this by throwing away samples.  Your DMA fifo might be timing out because its trying to transfer too much data, so decimation might help with this if that is the problem.

 

I did want to point out that changing the IO Mod Clock 0 properties rate only affects the FPGA compilation constrants checking.  You probably should set it to 100 MHz or 120 MHz.  I'm not sure if it will help with your DMA issue.  

 

I hope this helps.

Nathan

Product Support Engineer
National Instruments
Message 24 of 27
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Ok, this will definitly explain my DMA timeouts. I'll rewrite my code to throw away samples and recompile it.

Thanks again!

Bjorn

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Message 25 of 27
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Hey Nathan,

 

Thank you very much for your help! I've finally been able to get rid of the noise ripples.

You clarified some important things that at least from my point of view are not 100% clear from the NI5734 manual:

 

1. The SCTL which acquires the samples from the NI5734 has to be the IO Module Clock 0.

2. The IO Module Clock 0 always runs at 120 MHz regardless of what you specify for compilation

3. The only way to decrease the sampling rate is to throw away samples.

 

I rewrote my program to account for these three facts et voila, it is working without any problems!

I still don't understand why these ripples only occured once I accessed the gain but I guess it is not worth investigating this matter.

 

Thanks again!

Bjorn

 

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Message 26 of 27
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I'm glad that your code is now working, although I am stumped as to why changing the Gain settings would have mattered.  With this behavior, I would have expected it continuously during the acquisition.  

 

Also, your correct about not being able to change the sample rate, while you are using on onboard oscillator.  If you were to use an external source, you would be able to change the ADC sample rate. (see the NI5754 documenation for more information)  With the new rate you could change the IO Mod Clock properties to match the expected external clock rate, as doing so will adjust the timing analysis done during the FPGA compilation accordingly.  

 

I hope this helps!

-Nathan 

Product Support Engineer
National Instruments
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Message 27 of 27
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