Can't communicate with module in cRIO hybrid

[Jay6]

I've been developing a cRIO hybrid application (using FPGA and Scan Interface mode). I'm communicating with one module in FPGA mode, and 6 in Scan Interface mode. The host VI on the computer is pulling Scan Interface information from Shared Variables, and communicating with the single FPGA VI with a dynamic reference.

The issue I'm having is that seemingly randomly, communication with the Scan Interface modules stopped working, it throws error -66536. However, the communication works if I make a new Scan Interface project, or even just take the FPGA out the current one.

Things I've tried that didn't work:

- An NI application engineer suggested formatting and reinstalling the cRIO software.

- Making sure the FPGA reference is called before shared variable commmunication, and shut down after its done.

- Recompiling the FPGA VI

Unfortunately I can't share any code, its a large software, and protected by the project its under. I'd be happy to answer more detailed questions though.

Thanks.

[GerdW]

Hi Jay,

is it too much work to handle the remaining 6 modules in the FPGA too? That way you can get rid of the ScanEngine/Hybrid-mode at all. (In my experience handling all IO in the FPGA isn't that much work.)

Depending on the used modules you also gain some degrees of freedom: you could set different working modes for DIO modules, different sample speeds for single AI/AO pins, and so on…

[Jay6]

That's not a bad idea, however, I'm already using about 85% of the FPGA just running this one VI (its PWM with PID on a lot of heaters) so I don't think I have the capacity to implement that.

[GerdW]

Hi Jay,

you need to control heaters using PID on the FPGA? How fast do they react?

My heaters usually have time constants in the order of tens of seconds and can be handled by the RT target quite easily…

[Jay6]

Many of the PID thermal components are actually handling nitrogen flow, which needs to react very quickly. There's a pretty small range of error in temperature allowed.

Perhaps you're right though, but that's an issue to visit in more detail at a later time. I have a deadline tomorrow, and I'm just trying to get the software functionality back to how it was.

[fromm8]

Hi Jay

Just to double check one of the points you already covered. You mentioned: Things I've tried that didn't work: - Making sure the FPGA reference is called before shared variable communication, and shut down after its done.

About this point: I just want to check how you accomplished that... by just assuring the desired data flow or you also tested or tried to implement delays?

Regards

Frank R.