I am trying to use the Ethernet based reference architecture for USRP Rio.
But I'm unable to compile its FPGA VI due to the following error:
Component-level IP (CLIP) does not support the following .xci file, because this file is created by an old version of Xilinx compilation tools.
C:\Users\user\Desktop\USRP_RIO_Ethernet - v1.0\USRP\CLIP\10GbE\ten_gig_eth_pcs_pma_0.xci
Component-level IP (CLIP) supports only .xci files created by Vivado 2017.2.
I've got LabVIEW2019 and Vivado 2017.2 installed on my system, but I don't know how to regenerate that .xci file using Vivado 2017.2
Solved! Go to Solution.
I would try to:
But I am not familiar with LabVIEW.
Thanks tcachat for your suggestion, the problem seems to have been resolved.
As you suggested, I installed Vivado 2017.2. Fortunately, I happened to found the latest IP within the IP catalogue. So I generated outputs for that IP and it produced the latest .xci file I needed.
I added the updated IP file in LabVIEW and the error was gone.