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CLIP Synchronisation registers

I have a Socketed CLIP that we use in our FPGA project.  We've been using it for years.

 

We recently did some refactoring of our CLIP and did some benchmarking to verify resource savings through the refactoring work.  We received different results than expected.  It appears that the synchronisation registers defined in the LV Project are being optimised away.  We are not writing to / reading from hardware directly, there is VHDL logic in between.  Can it be that Xilinx decides to simply remove these registers as it sees fit?  Our clocks on write / read nodes are phase related with the CLIP clock, but they are not the SAME clock (The have the same base clock).

 

We are currently investigating a decign where latency to and from CLIP is critical and the idea of Xilinx meddling with this aspect of our code makes me very uneasy (it actually scares me).

 

I did a small test VI where I simply read from our CLIP and write to controls and I see the expected resource difference with 2 Read sync registers and with none.  Even utilising a related clock does not cause the registers to be removed.  Interesting is that the resource differences in pre-synthesis are 2 registers, synthesis only 1 and the final again 2..... (1080 registers, 540 registers and 1080 registers). Smiley Frustrated

 

Does anyone have experience with this?

 

All work done on Virtex 5 (ISE 14.7) with LV 2015 SP1.

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Hello Intaris,

 

I was recently teaching our Embedded Control and Monitoring course. In which we discuss enable inputs, we mention that a SCTL will result in automatic removal of the enable inputs and hence everything runs within one tick. You mentioned a VI but then also socketed CLIP, if you run your code within an SCTL in a VI then this could be the cause of your issue.

 

However I do need to refresh my memory on this as it has been a while since I played around with VHDL, Socket CLIP and FlexRIO (I assume you are using FlexRIO?). Anyway, one thing I did look into back then was this document:

 

http://zone.ni.com/reference/en-XX/help/371599H-01/lvfpgaconcepts/fpga_sctl_and_synchro/

 

If I remember correctly, you configure synchronisation registers by right clicking the IO node of your CLIP and selecting properties, you should then find a category to set this.

 

http://zone.ni.com/reference/en-XX/help/371599K-01/lvfpgadialog/fpga_io_advcodegen_db/

 

Additionally are you using case structures within your code where you use the IO? If I remember correctly this can cause issues with synchronisation registers and essentially remove them.

 

Could you possibly provide how you are confirming this behaviour and documentation on this, your LV project or a small version which demonstrates the issue and your VHDL code?

 

Best regards,


Ed

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