I'm evaluating compact RIO. I would like to use it as variable functionality hardware.
I have the need to change it's behavior in two ways:
1. By loading different RT and FPGA VIs from non LabView environment. I have seen "C Interface to LabVIEW FPGA" which loads FPGA bit file. What about RT?
states it is possible to program the real-time processor.
So, can I develop multiple RT and FPGA VIs with LabView and afterwards upload them to cRIO in C++ application. If yes, is "C Interface to LabVIEW FPGA" library right way to go or are others? Or is the RT processor the one enabling library interface to FPGA an so can't be used for anything else when in this mode?
2. Once the RT and FPGA are loaded I would access variables (as parameters to functionality) over STM or network shared variables - don't know which yet - which is better?
In both attached I/Os would be the same... not that it matters I belive.
In short, I'm seeking the way to control (load, strat, stop and read/write variables) the cRIO within C++ project runuing on Windows host.
I'm interested in creating FPGA VI like you suggested (with LabVIEW FPGA Module) and also functionality for embedded real-time processor with LabVIEW Real-Time Module that interconnects with FPGA if I understood correctly. I can implement STM in RT processor if I chose to. After both are transferred to cRIO it can function as standalone hardware which is what I want, and I can communicate with it when I need to read or set variables exposed over STM.
Question here is: can I upload another RT-FPGA pair (again both designed with LV) to make different standalone hardware without LabVIEW (with C++)?
Well, that's a totally different question than what you were asking.
I have not tried it but I don't think you will be able to do it unless someone can correct me. The reason is that you will need to stop the former RT VI and then run the new RT VI once you manage to upload it to the cRIO controller, both of which I am not sure you can do from an external environment like C++. Also, the former RT VI will need to stop the former FPGA and the new RT VI will need to download the new FPGA VI on the backplane of the cRIO and run it. The only thing you CAN probably do is use the C++ environment to transfer the new RT-FPGA pair to the cRIO's non-volatile memory but, like I said before, I am not sure if you will be able to run the new RT VI or stop the old RT VI from that environment. It's easy to do so from LabVIEW using VI Server.
Thanks for your time so far!
I assumed it won't be easy as I imagined after not hitting any search result after hours of browsing.
So, assuming I have functional standalone cRIO connected to network over TCP/IP, what are my possibilities for accessing variables?
I know about shared variables and STM. Are there any other interfaces/libraries?
Which way is preferred to use from C++ environment?